TL16C552 datasheet(21/33 Pages) TI1

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TL16C552

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B − DECEMBER 1990 − REVISED MARCH 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

line control register (LCR)

The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described

in the following bulleted list and shown in Figure 17.

D Bits 0 and 1: LCR0 and LCR1 are the word length select bits. The number of bits in each serial character

is programmed as shown in Figure 17.

D Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character

as shown in Figure 17. The receiver always checks for one stop bit.

D Bit 3: LCR3 is the parity enable bit 3. When LCR3 is high, a parity bit between the last data word bit and

stop bit is generated and checked.

D Bit 4: LCR4 is the even parity select bit 4. When enabled, setting this bit selects even parity.

D Bit 5: LCR5 is the stick parity bit 5. When parity is enabled (LCR3=1), LCR5=1 causes the transmission

and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity to a known

state and allows the receiver to check the parity bit in a known state.

D Bit 6: LCR6 is the break control bit 6. When LCR6 is set, the serial output (SOUT1 and SOUT0) is forced

to the spacing state (low). The break control bit acts only on the serial output and does not affect the

transmitter logic. When the following sequence is used, no invalid characters are transmitted because of

the break:

Step 1. Load a zero byte in response to the transmitter holding register empty (THRE) status indication.

Step 2. Set the break in response to the next THRE status indication.

Step 3. Wait for the transmitter to be idle when transmitter empty status signal is set high (TEMT=1). Then

clear the break when the normal transmission has to be restored.

D Bit 7: LCR7 is the divisor latch access bit (DLAB) bit 7. Bit 7 must be set to access the divisor latches DLL

and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the

receiver buffer register, the transmitter holding register or the interrupt enable register.

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