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LMH6503MT/NOPB датащи(PDF) 21 Page - Texas Instruments

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номер детали LMH6503MT/NOPB
подробное описание детали  LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
PDF  33 Pages
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LMH6503MT/NOPB датащи(HTML) 21 Page - Texas Instruments

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LMH6503
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SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
CIRCUIT LAYOUT CONSIDERATIONS
Good high-frequency operation requires all of the de-coupling capacitors shown in Figure 64 to be placed as
close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass.
Adequate ground plane and low inductive power returns are also required of the layout. Minimizing the parasitic
capacitances at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency performance. The parasitic
inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load
capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or
circuit oscillation. The LMH6503 is fully stable when driving a 100
Ω load. With reduced load (e.g. 1kΩ) there is a
possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the
LMH6503 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g.
100
Ω and 39pF in series tied between the LMH6503 output and ground). CL can also be isolated from the output
by placing a small resistor in series with the output (pin 10).
Figure 64. Required Power Supply Decoupling
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board Part Number
LMH6503MA
SOIC-14
LMH730033
SINGLE SUPPLY OPERATION
It is possible to operate the LMH6503 with a single supply. To do so, tie pin 11 (GND) to a potential about mid
point between V+ and V−. Two examples are shown in Figure 65 & Figure 66.
Copyright © 2003–2013, Texas Instruments Incorporated
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