TUSB5052PZ datasheet(59/82 Pages) TI

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7−11

7.2.4

Auto-CTS (Transmitter Control)

In this mode the CTS input pin controls the transfer from internal buffer (X or Y) to the TDR. When the DMA controller

transfers data from the Y-buffer to the TDR and the CTS input pin goes high, the DMA controller is suspended until

CTS goes low. Meanwhile, the UBM is transferring data from the host to the X-buffer. When CTS goes low, the DMA

resumes the transfer. Data transfer continues alternating between the X and Y buffers, without MCU intervention. See

Section 6.2 for DMA transfer termination conditions.

7.2.5

Xon/Xoff Receiver Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the Xon/Xoff bytes are transmitted to an external sending device to control the device transmission. When the

high-level mark (of the FIFO) is reached, the Xoff byte is transmitted, signaling to an external sending device to halt

its transfer. Conversely, when the low-level mark is reached, the Xon byte is transmitted, signaling to an external

sending device to resume its transfer. Data transfer from the FIFO to X/Y-buffer is performed by the DMA controller.

7.2.6

Xon/Xoff Transmitter Flow Control

To enable Xon/Xoff flow control, certain MCR bits must be set as follows: MCR[5] = 1 and MCR[7:6] = 0. In this mode,

the incoming data are compared to the XON and XOFF registers. If a match to XOFF is detected, the DMA is paused.

If a match to XON is detected, the DMA resumes. Meanwhile, the UBM is transferring data from the host to the

X-buffer. The MCU does not switch the buffers unless the Y-buffer is empty and X-buffer is full. When Xon is detected,

the DMA resumes the transfer.

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