Data

Direction

Bit 0

Data

Bit 1

1

Bit 2

1

Bit 3

1

Bit 4

1

Bit 5

1

Bit 7

1

Bit 6

MSB

LSB

GPIO Register

Register Address 0x81

Power On Reset = 0xFC

HWEN

Enable/

Disable

Bit 0

Frequency

Selection

Bit 7

MSB

LSB

HWEN/PGENGPIO Register

Register Address 0x80

Power On Reset = 0x01

Frequency

Selection

Bit 6

Duty Cycle

Selection

Bit 5

Duty Cycle

Selection

Bit 4

GPIO

Data

Bit 2

Duty Cycle

Selection

Bit 3

GPIO

Data

Direction

Bit 1

LM3528

www.ti.com

SNVS513B – AUGUST 2008 – REVISED MAY 2013

Table 6. HPG Register Function

Bits 5 - 3 (PGEN

Bits 7 – 6

Bit 2

Bit 1 (GPIO

Bit 0

Enable/Disable and

(PGEN Bit

(GPIO

Data

(HWEN

Function

Duty Cycle

Period)

Data)

Direction)

Control)

Selection)

X

X

X

X

0

HWEN/PGEN/GPIO is configured as an active high

Hardware Enable Input (HWEN)

X

X

1

HWEN/PGEN/GPIO is configured as a Pattern Generator

00 = 1.6µs/bit 001 = 100%

Output with the frequency set by bits <7:6> and the duty

(625kHz)

010 = 1/2

cycle set by bits <5:3>. (See Figure 46.)

01 = 26ms/bit 011 = 1/3

(38Hz)

100 = 1/4

10 = 52ms/bit

101 = 1/6

(19Hz)

110 = 1/12

11 = 105ms/bit

(9.5Hz)

111 = Latch Pattern

(1)

Into Shift Register

(2)

X

000

GPIO

1

1

HWEN/PGEN/GPIO is configured as a GPIO Input. Read

Read Data

data from bit 2.

X

000

GPIO

0

1

HWEN/PGEN/GPIO is configured as a GPIO Output. A ‘1’

Write Data

written to bit 2 will force HWEN/PGEN/GPIO high; a 0

written to bit 2 will force HWEN/PGEN/GPIO low.

(1)

This represents the amount of time each programmed bit will be present at HWEN/PGEN/GPIO. The entire pattern period will be 32 ×

Bit Period.

(2)

This duty cycle indicates the fraction of time the pattern is being output at HWEN/PGEN/GPIO. For example the 1/2 duty cycle (bits

<5:3> = 010) will have the 32 bit pattern output once followed by a dead time (HWEN/PGEN/GPIO high impedance) equal to 1×’s the

pattern period (Deadtime = 32 × Bit_Period × (1/DutyCycle -1). For the 100% duty cycle setting the 32 bit pattern will repeat constantly

with no deadtime.

Figure 45. HPG Register Description

Table 7. GPIO Register Function

Bits 7 - 2

GPIO Data (Bit 1)

Data Direction (Bit 0)

Function

X

X

0

GPIO is configured as a GPIO

input with the input data read

back via bit [1]. This is the default

power on state.

X

X

1

GPIO is configured as a logic

output. The output logic voltage

is written to bit [1].

Figure 46. GPIO Register Description

Figure 47 – Figure 50 detail the Pattern Generator Data Registers. These hold the 32 bit data that is output at

HWEN/PGEN/GPIO in PGEN mode. The data is output LSB first (Bit 0 of PGEN0) and MSB last (Bit 7 of

PGEN3).

Copyright © 2008–2013, Texas Instruments Incorporated

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