A1

A2

B1

B2

B3

Top View

A3

C2

C1

C3

D2

D1

D3

LM3528

SNVS513B – AUGUST 2008 – REVISED MAY 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

low voltage output capacitors. Other features include a dedicated general purpose I/O (GPIO) and a multi-

function pin (HWEN/PGEN/GPIO) which can be configured as a 32 bit pattern generator, a hardware enable

compatible interface and output at HWEN/PGEN/GPIO for indicator LED flashing or for external logic control.

The LM3528 is offered in a tiny 12-bump DSBGA package and operates over the -40°C to +85°C temperature

range.

Connection Diagram

Figure 3. 12-Bump (1.215mm × 1.615mm × 0.6mm) YFQ0012

PIN DESCRIPTIONS

Pin

Name

Function

A1

OVP

Over-Voltage Protection Sense Connection. Connect OVP to the positive terminal of the output

capacitor.

A2

MAIN

Main Current Sink Input.

A3

SUB/FB

Secondary Current Sink Input or 1.21V Feedback Connection for Constant Voltage Output.

B1

GPIO1

Programmable General Purpose I/O.

B2

SCL

Serial Clock Input

B3

SET

LED Current Setting Connection. Connect a resistor from SET to GND to set the maximum LED

C1

HWEN/PGEN/GPI

Active High Hardware Enable Input. Programmable Pattern Generator Output, and Programmable

O

General Purpose I/O.

C2

SDA

Serial Data Input/Output

C3

IN

Input Voltage Connection. Connect IN to the input supply, and bypass to GND with a 1µF ceramic

capacitor.

D1

VIO

Logic Voltage Level Input

D2

SW

Drain Connection for Internal NMOS Switch

D3

GND

Ground

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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