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LVCMOS

10 pF

Y3

CDCM1804

1 k

Ω

1 k

Ω

S0079-02

PCB DESIGN FOR THERMAL FUNCTIONALITY

CDCM1804

SCAS697E – JULY 2003 – REVISED MAY 2005

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 10. LVCMOS Output Loading During Device Test

It is recommended to take special care of the PCB design for good thermal flow from the QFN-24 terminal

package to the PCB.

Due to the three LVPECL outputs, the current consumption of the CDCM1804 is fixed.

JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.

Modeling the CDCM1804 with a standard 4-layer JEDEC board results in a 67.22

°C maximum temperature with

When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 46.94

°C

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling all

four outputs at once.

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