SN65LVDS311

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SLLSE31B – MAY 2010 – REVISED MARCH 2013

RECOMMENDED OPERATING CONDITIONS

(1)

MIN

NOM

MAX

UNIT

Supply voltages

1.65

1.8

1.95

V

Test set-up see Figure 10

f(PCLK)

≤ 50MHz; f(noise) = 1 Hz to 2 GHz

100

Supply voltage noise

mV

magnitude (all supplies)

f(PCLK) > 50MHz; f(noise) = 1 Hz to 1MHz

100

f(PCLK) > 50MHz; f(noise) > 1MHz

40

1-Channel transmit mode, see Figure 1

4

15

2-Channel transmit mode, see Figure 2

8

30

Pixel clock frequency

MHz

3-Channel transmit mode, see Figure 3

20

65

Frequency threshold Standby mode to active

0.5

3

PCLK input duty cycle

0.33

0.67

Operating free-air

–40

85

°C

temperature

5

ps-rms

PCLK total jitter

s

Measured on PCLK input

PCLK peak

s

PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP

High-level input voltage

V

Low-level input voltage

V

Data set up time prior to

2.0

ns

PCLK transition

f (PCLK) = 65MHz; see Figure 6

Data hold time after PCLK

2.0

ns

transition

(1)

Unused single-ended inputs must be held high or low to prevent them from floating.

(2)

PCLK input frequencies lower than 500kHz force the SN65LVDS311into standby mode. Input frequencies between 500kHz and 3MHz

may or may not activate the SN65LVDS311. Input frequencies beyond 3MHz activate the SN65LVDS311.

(3)

Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.

(4)

Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle

pairs.

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