SN65LVDS311 Top view

SN65LVDS311 Bottom view

7

6

4

5

3

2

1

A

D

C

B

G

F

E

R5

G6

D2P

G7

GND

V

DDPLLA

D0N

V

DDPLLD

TXEN

GND

VDD

GND

GND

CLKP

G4

GND

R6

R7

G5

LS0

D0P

B1

B3

B5

B4

GND

CLKN

D1N

D1P

R3

LS1

G2

B0

D2N

B2

VS

B7

G0

R0

R2

R1

HS

DE

PCLK

B6

R4

G1

G3

A

D

C

B

G

F

E

2

G6

G7

R6

B5

G2

R2

R1

1

R5

G4

G5

B1

B4

R3

B0

3

D0N

R7

B3

B2

R0

G1

G3

4

VDD

GND

GND

GND

D0P

B7

G0

7

D2P

D1N

D1P

D2N

HS

PCLK

6

GND

V

DDPLLA

CLKP

LS0

GND

VS

DE

5

V

DDPLLD

TXEN

GND

CLKN

LS1

B6

R4

TXEN

PCLK

VS

HS

B[0:7]

G[0:7]

R[0:7]

DE

LS1

8

8

8

SubLVDS

D0+

D0-

SubLVDS

D2+

D2-

SubLVDS

CLK+

CLK-

SubLVDS

D1+

D1-

LS0

iPCLK

Glitch

Suppression

Control /

Standby Monitor

Bit 29

Bit 28 = 0

Bit 27 = 0

[0..26]

Parity

Calculation

x10, x15, x30

x1

PLL

Multiplier

SN65LVDS311

SLLSE31B – MAY 2010 – REVISED MARCH 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Functional Block Diagram

PINOUT

2

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