ATMEGA88 datasheet(17/349 Pages) ATMEL

17 / 349 page

ATmega48/88/168

2545D–AVR–07/04

Figure 10. Data Memory Map

Data Memory Access Times

This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk

CPU cycles as described in Figure

11.

Figure 11. On-chip Data SRAM Access Cycles

EEPROM Data Memory

The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is

organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access

between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control

“Memory Programming” on page 270 contains a detailed description on EEPROM Pro-

gramming in SPI or Parallel Programming mode.

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 3. A self-timing function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, V

CC is likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

32 Registers

64 I/O Registers

Internal SRAM

(512/1024/1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x02FF/0x04FF/0x04FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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