WM8750 datasheet(37/60 Pages) WOLFSON

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Production Data

WM8750BL

PD, Rev 4.1, August 2012

LINE OUTPUT

The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs. Additionally,

OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg. 24) and

ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35 (left out

mix). Recommended external components are shown below.

Figure 15 Recommended Circuit for Line Output

The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc.

Assuming a 10 kOhm load and C1, C2 = 1

F:

fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz

Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will

diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage

when used improperly.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data into the WM8750BL and outputting ADC

data from it. It uses five pins:



ADCDAT: ADC data output



ADCLRC: ADC data alignment clock



DACDAT: DAC data input



DACLRC: DAC data alignment clock



BCLK: Bit clock, for synchronisation

The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750BL operates as a

master, or inputs when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:



Left justified



DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8750BL can be configured as either a master or slave mode device. As a master device the

WM8750BL generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data

transfer on ADCDAT and DACDAT. In slave mode, the WM8750BL responds with data to clocks it

receives over the digital audio interface. The mode can be selected by writing to the MS bit (see

Table 23). Master and slave modes are illustrated below.

Figure 16 Master Mode

Figure 17 Slave Mode

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