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SLK2501

SLLS502C – OCTOBER 2001 – REVISED MARCH 2007

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

CLOCK PINS

REFCLKP

94

LVDS/PECL

Differential reference input clock. There is an on-chip 100-

Ω termination resistor

REFCLKN

95

compatible input

differentially placed between REFCLKP and REFCLKN. The dc bias is also provided

on-chip for the ac-coupled case.

TXCLKP

79

LVDS input

Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of

TXCLKN

80

TXCLKP.

TXCLKSRCP

70

LVDS output

Transmit clock source. A clock source generated from the SLK2501 device to the

TXCLKSRCN

71

downstream device (i.e., framer) that could be used by the downstream device to

transmit data back to the SLK2501 device. This clock is frequency-locked to the local

reference clock.

RXCLKP

67

LVDS output

Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The

RXCLKN

68

interface of RXDATA(0:3) and RXCLKP is source synchronous (refer to Figure 7).

SERIAL SIDE DATA PINS

STXDOP

9

PECL compatible

Transmit differential pairs; high-speed serial outputs

STXDON

8

output

SRXDIP

14

PECL compatible

Receive differential pairs; high-speed serial inputs

SRXDIN

15

input

PARALLEL SIDE DATA PINS

TXDATA[0:3]

88-81

LVDS input

Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP.

P/N

TXDATA0 is the first bit transmitted in time.

TXPARP

99

LVDS input

Transmit data parity input

TXPARN

98

RXDATA[0:3]

66-63

LVDS output

Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP

P/N

60-57

(refer to Figure 7). RXDATA0 is the first bit received in time.

RXPARP

56

LVDS output

Receive data parity output

RXPARN

55

FSYNCP

73

LVDS output

Frame sync pulse. This signal indicates the frame boundaries of the incoming data

FSYNCN

74

stream. If the frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and

RXCLKN clock cycles, when it detects the framing patterns.

CONTROL/STATUS PINS

RSEL0

39

TTL input (with

Data rate configuration pins. Put the device under one of the four data rate operations:

RSE1L

38

pulldown)

OC-48, OC-24, OC-12, or OC-3.

CONFIG0

17

TTL input (with

Configuration pins. Put the device under one of the four operation modes: TX only, RX

CONFIG1

18

pulldown)

only, transceiver, or repeater mode. (See Table 3)

PRE1

4

TTL input (with

Programmable de-emphasis control. Combinations of these two bits can be used to

PRE2

5

pulldown)

optimize serial data transmission.

RESET

48

TTL input (with

TXFIFO and LOL reset pin. Low is reset and high is normal operation.

pulldown)

AUTO_DETECT

34

TTL input (with

Data rate autodetect enable. Enable the autodetection function for different data rates.

pulldown)

When AUTO_DETECT is high, the autodetection circuit generates RATEOUT0 and

RATEOUT1 to indicate the data rates for the downstream device.

LLOOP

53

TTL input (with

Local loopback enable. When this pin is high, the serial output is internally looped back

pulldown)

to its serial input.

RLOOP

54

TTL input (with

Remote loopback enable. When this pin is high, the serial input is internally looped back

pulldown)

to its serial output with the timing extracted from the serial data.

ENABLE

44

TTL input (with

Standby enable. When this pin is held low, the device is disabled for IDDQ testing.

pullup)

When high, the device operates normally.

FRAME_EN

27

TTL input (with

Frame sync enable. When this pin is asserted high, the frame synchronization circuit for

pullup)

byte alignment is turned on.

PRBSEN

41

TTL input (with

PRBS testing enable. When this pin is asserted high, the device is put into the PRBS

pulldown)

testing mode.

SIGDET

20

TTL input (with

Signal detect. This pin is generally connected to the output of an optical receiver. This

pulldown)

signal may be active high or active low depending on the optical receiver. The SIGDET

input is XORed with the PS pin to select the active state. When SIGDET is in the

inactive state, data is processed normally. When activated, indicating a loss of signal

event, the transmitter transmits all zeroes and force the LOS signal to go high.

4

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