DP83924 datasheet(18/42 Pages) NSC

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3.0 Detailed Functional Description (Continued)

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negotiate to 10Mb/s Half Duplex operation by detecting link

pulses separated by 8-24 ms.

3.4.20 Auto-Negotiation Restart

Once Auto-Negotiation has completed it may be restarted

at any time byfirst resetting and then setting bit 9 of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu-

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

A renegotiation request fromany entity, such as a manage-

ment agent, will cause the 4TPHY to halt any transmit data

and link pulse activity until the break_link_timer expires

(1500ms). Consequently, the Link Partner will go into link

fail and normal Auto-Negotiation resumes. The 4TPHY will

resume Auto-Negotiation after the break_link_timer has

expired by issuing FLP (fast Link Pulse) bursts.

3.4.21 Enabling Auto-Negotiation via Software

It is important to note that if the 4TPHY has been initialized

upon power-up as a non-auto-negotiating device (forced

technology), and it is then required that auto-negotiation of

re-auto-negotiation be initiated via software, bit 0 of the

Basic Mode Control Register must first be cleared and then

set for any auto-negotiation function to take effect.

3.5 JTAG Boundary Scan

The 4TPHY supports JTAG Boundary Scan per IEEE

1149.1 via test clock (TCK), test data input (TDI), test data

output (TDO), test mode select (TMS), and test reset

(TRST). The IEEE 1149.1 standard defines a test access

port and boundary-scan architecture for digital integrated

circuits and for the digital portions of mixed analog/digital

integrated circuits. Figur e12 depicts the IEEE 1149.1

architecture

The standard provides a solution for testing assembled

printed circuit boards and other products based on highly

complex digital integrated circuits and high-density surface-

mounting assembly techniques. It also provides a means of

accessing and controlling design-for-test features built into

the digital integrated circuits. Such features include internal

scan paths and self-test functions as well as other features

intended to support service applications in the assembled

product. The IEEE 1149.1 Boundary Scan Architecture

document should be referenced for additional detail.

The

circuitry defined by

this

standard

allows test

instructions and associated data to be input serially into a

device. The instruction execution results are output serially.

The DP83924B reserves five pins, called the Test Access

Port (TAP), to provide test access: TMS, TCK, Test Data

Input (TDI), Test Data Output (TDO) and Test Reset

(TRST). These signals are describe d in T able4 on page7.

To ensure race-free operation all input and output data is

synchronous to the test clock (TCK). TAP input signals

(TMS and TDI) are clocked into the test logic on the rising

edge of TCK while output signal (TDO) is clocked on the

falling edge.

3.5.22 Test Logic

The IEEE 1149.1 Test Logic consists of a Test Access Port

(TAP) controller, an instruction register, and a group of test

data registers including Bypass, Device Identification and

Boundary Scan registers.

TheTAP controller is a synchronous 16 state machine that

responds to changes at the TMS and TCK signals.

This controls the sequence of operations by generating

clock and control signals to the instruction and test data

registers. The control signals switch TDI and TDO between

instruction and test data registers

The DP83924B implements 4 basic instructions: ID_Code,

bypass, Sample/Preload and Extest. Upon reset, the

ID_Code instruction is selected by default.

Figure 11. Auto-Negotiation Block Diagram

10BASE-T

Transceiver

10BASE-T

Transceiver

10BASE-T

Transceiver

10BASE-T

Transceiver

Auto-negotiation

Block

Auto-negotiation

Block

Auto-negotiation

Block

Auto-negotiation

Block

Timer Block

To Registers

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