DP83924 datasheet(7/42 Pages) NSC

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1.0 Pin Information (Continued)

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Table 3. LED & GENERAL CONFIGURATION Pins (8 Pins)

Symbol

Pins

Type

Description

LED_DATA

LED serial data output: This pin outputs the serial LED data. See S ection2.3 for a de-

scription of the LED modes. This output should be connected to the input of the 1st (ex-

ternal) serial shift register.

LED_CLK

LED Clock: This is the clock for the serial shift registers

External Oscillator Input: This signal is used to provide clocking signals for the internal

ENDEC. A 20MHz oscillator module should be used to drive this pin.

RESET

Reset: Active low input resets the transceiver, and starts the initialization of the device.

This pin has a noise filter on it’s input, which requires that the reset pulse must be greater

than 30 X1 clocks.

FDX[4:1]

38 -35

Full Duplex: These pins are sampled during reset. They control the full duplex (or half

duplex) configuration of each port. If pulled low, Full Duplex operation is selected for the

respective port. If pulled high, Half Duplex operation is selected. These pins have no in-

ternal pull-up or pull-down resistors.These pins are also used in “Enhanced full duplex”

mode to dynamically select Full/Half duplex mode of operat i on. See Section3.3.14

Table 4. SCAN TEST Pins (5 Pins)

Symbol

Pins

Type

Description

TCK

Test Clock: This signal is used during boundary scan to clock data in and out

of the device.

TDI

Test Input: The signal contains serial data that is shifted into the device by the

TAP controller. An internal pullup is provided if not used. It is recommended that

during normal transceiver operation a ‘1’ should be applied to this pin.

TDO

O,Z

Test Output:The tristateable signal contains serial data that is shifted out of the

device by the TAP controller.

TMS

Test Mode Select: This selects the operation mode of the TAP controller. An

internal pullup is provided if not used

TRST

Test Reset: When this signal is asserted low it forces the TAP (Test Access

Port) controller into a logic reset state. An internal pullup is provided. This pin

should be pulled low during normal transceiver operation.

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