ADS8364YSLASH2K datasheet(13/22 Pages) TI

13 / 22 page

ADS8364

SBAS219B

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EOC

—End of conversion goes low when new data of the

internal ADC is latched into the output registers, which

usually happens 16.5 clock cycles after hold initiated the

conversion. It remains low for half a clock cycle. If more than

one channel pair is converted simultaneously, the

A-channels get stored to the registers first (16.5 clock cycles

after hold), followed by the B-channels one clock cycle later,

and finally the C-channels at another clock cycle later. If a

reading (RD and CS are LOW) is in process, then the latch

process is delayed until the read operation is finished.

FD—First data or A0 data is HIGH if channel A0 is chosen to be

read next. In the FIFO mode whatever channel X0 is written to

the FIFO first is latched into the A0 register. So, for example,

when the FIFO is empty, FD is 0. Then the first result is latched

into the FIFO register A0 is, therefore, chosen to be read next,

and FD rises. After the first channel is read (1-3 read cycles

depending on BYTE and ADD) FD goes LOW again.

START OF A CONVERSION AND READING DATA

By bringing one, two, or all of the HOLDX signals LOW, the

input data of the corresponding channel X is immediately

placed in the hold mode (5ns). The conversion of this channel

X follows with the next rising edge of clock. If it is important to

detect a hold command during a certain clock-cycle, then the

falling edge of the hold signal has to occur at least 10ns before

the rising edge of clock, as shown in Figure 7, tD1. The hold

signal can remain LOW without initiating a new conversion.

The hold signal has to be HIGH for at least 15ns (as shown

in Figure 7, tW2) before it is brought LOW again and hold has

to stay LOW for at least 20ns (Figure 7, tW3).

Once a particular hold signal goes low, further impulses of

this hold signal are ignored until the conversion is finished or

the part is reset. When the conversion is finished (after 16

clock cycles) the sampling switches will close and sample the

selected channel. The start of the next conversion must be

delayed to allow the input capacitor of the ADS8364 to be

fully charged. This delay time depends on the driving ampli-

fier, but should be at least 800ns.

FIGURE 7. Start of the Conversion.

The ADS8364 can also convert one channel continuously

(see Figure 8). Therefore, HOLDA and HOLDC are kept

HIGH all the time. To gain acquisition time, the falling edge

of HOLDB takes place just before the rising edge of clock.

One conversion requires 20 clock cycles. Here, data is read

after the next conversion is initiated by HOLDB. To read data

from channel B, A1 is set HIGH and A2 is LOW. As A0 is

LOW during the first reading (A2 A1 A0 = 010) data B0 is put

to the output. Before the second RD, A0 switches HIGH (A2

A1 A0 = 011) so data from channel B1 is read, as shown in

Table II. However, reading data during the conversion or on a

falling hold edge might cause a loss in performance.

CHANNEL TO BE READ

CHA0

CHA1

CHB0

CHB1

CHC0

CHC1

Cycle mode reads registers

CHA0 through CHC1 on

successive transitions of the

read line.

FIFO Mode

TABLE II. Address Control for RD Functions.

Reading data (RD, CS )—In general, the channel/data

outputs are in tri-state. Both CS and RD have to be LOW to

enable these outputs. RD and CS have to stay LOW to-

gether for at least 40ns (see Timing Characteristics, tD6)

before the output data is valid. RD has to remain HIGH for

at least 30ns (see Timing Diagram, tW5) before bringing it

back LOW for a subsequent read command.

16.5 clock-cycles after the start of a conversion (next rising

edge of clock after the falling edge of HOLDX ), the new data

is latched into its output register. Even if the ADS8364 is

forced to wait until the read process is finished (RD signal

going HIGH) before the new data gets latched into its output

CLK

HOLD A

RESET

HOLD B

HOLD C

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