DSD1796DBRG4 datasheet(6/61 Pages) TI1

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DSD1796

SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006

www.ti.com

Terminal Functions

TERMINAL

I/O

DESCRIPTIONS

NAME

I/O

DESCRIPTIONS

AGND1

–

Analog ground (internal bias)

AGND2

–

Analog ground (internal bias)

AGND3L

–

Analog ground (L-channel DACFF)

AGND3R

–

Analog ground (R-channel DACFF)

DBCK

Bit clock input for DSD mode (1)

DGND

–

Digital ground

DSDL

I/O

L-channel audio data input for DSD mode

PCM mode zero flag for L-channel when in zero-flag output mode(2)

DSDR

I/O

R-channel audio data input for DSD mode

PCM mode zero flag for R-channel when in zero-flag output mode (2)

IOUTL+

L-channel analog current output +

IOUTL–

L-channel analog current output –

IOUTR+

R-channel analog current output +

IOUTR–

R-channel analog current output –

IREF

–

Output current reference bias pin

Mode control clock input(1)

MDI

Mode control data input (1)

MDO

Mode control readback data output (3)

I/O

Mode control chip-select input(2)

PBCK

Bit clock input for PCM mode (1)

PDATA

Serial audio data input for PCM mode (1)

PLRCK

Left and right clock (fS) input for PCM mode (1)

RST

Reset(1)

SCK

System clock input (1)

VCC1

–

Analog power supply, 5 V

VCC2L

–

Analog power supply (L-channel DACFF), 5 V

VCC2R

–

Analog power supply (R-channel DACFF), 5 V

VCOML

–

L-channel internal bias decoupling pin

VCOMR

–

R-channel internal bias decoupling pin

VDD

–

Digital power supply, 3.3 V

(1) Schmitt-trigger input, 5-V tolerant

(2) Schmitt-trigger input and output. 5-V tolerant input, and CMOS output

(3) 3-state output

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