DSD1796DBRG4 datasheet(27/61 Pages) TI1

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DSD1796

SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006

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OS[1:0]: Delta-Sigma Oversampling Rate Selection

These bits are available for read and write.

Default value: 00

OS[1:0]

Operation Speed Select

64 times fS (default)

32 times fS

128 times fS

Reserved

The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer

to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming

to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use

of only a single type (cutoff frequency) of post low-pass filter. The 128-fS oversampling rate is not available at sampling rates

above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than 256 fS is required.

In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.

B15

B14

B13

B12

B11

B10

R/W

RSV

DZ1

DZ0

PCMZ

R/W: Read/Write Mode Select

When R/W = 0, a write operation is performed.

When R/W = 1, a read operation is performed.

Default value: 0

DZ[1:0]: DSD Zero Output Enable

These bits are available for read and write.

Default value: 00

DZ[1:0]

Zero Output Enable

Disabled (default)

Even pattern detect

96h pattern detect

The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The

DSD1796 sets zero flags when the numbers of 1s and 0s are equal in every 8 bits of DSD input data, or the DSD input data

is 1001 0110 continuously for 23 ms.

PCMZ: PCM Zero Output Enable

These bits are available for read and write.

Default value: 1

PCMZ = 0

PCM zero output disabled

PCMZ = 1

PCM zero output enabled (default)

The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The DSD1796

sets the zero flags when the input data is continuously zero for 1024 PLRCKs in the PCM mode or 1024 WDCKs in the

external filter mode.

B15

B14

B13

B12

B11

B10

RSV

ZFGR

ZFGL

R: Read Mode Select

Value is always 1, specifying the readback mode.

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