ADC121S101/ADC101S101/ADC081S101 Timing Specifications

The following specifications apply for V

all other limits T

Symbol

Parameter

Conditions

Typical

Limits

Units

t

CONVERT

16xt

SCLK

t

QUIET

(Note 7)

50

ns (min)

t

1

Minimum CS Pulse Width

10

ns (min)

t

2

CS to SCLK Setup Time

10

ns (min)

t

3

Delay from CS Until SDATA

20

ns (max)

t

4

Data Access Time after SCLK Falling

Edge(Note 9)

V

40

ns (max)

V

20

ns (max)

t

5

SCLK Low Pulse Width

0.4 x

t

SCLK

ns (min)

t

6

SCLK High Pulse Width

0.4 x

t

SCLK

ns (min)

t

7

SCLK to Data Valid Hold Time

V

7

ns (min)

V

5

ns (min)

t

8

SCLK Falling Edge to SDATA High

Impedance (Note 10)

V

25

ns (max)

6

ns (min)

V

25

ns (max)

5

ns (min)

t

POWER-UP

Power-Up Time from Full

Power-Down

1µs

Note 1: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional

operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may affect device reliability.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified

Note 3: Specification limit guaranteed by design.

Note 4: See the section titled "Surface Mount" found in a current National Semiconductor Linear Databook for other methods of soldering suface mount devices.

Note 5: Except power supply pins.

Note 6: Independent of supply voltage.

Note 7: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion

Note 8: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.

Note 9: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.

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