ADC101S101 datasheet(19/23 Pages) NSC

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Applications Information (Continued)

4.0 SAMPLE CIRCUIT

A typical application of the ADC121S101/101S101/081S101

is shown in Figure 8. The combined analog and digital

supplies are provided in this example by the National

LP2950 low-dropout voltage regulator, available in a variety

of fixed and adjustable output voltages. The supply is by-

passed with a capacitor network located close to the device.

The three-wire interface is also shown connected to a micro-

processor or DSP.

5.0 ANALOG INPUTS

equivalent

circuit

for

the

ADC121S101/101S101/

081S101 input channel is shown in Figure 9. The diodes D1

and D2 provide ESD protection for the analog inputs. At no

time should an analog input exceed V

DD + 300 mV or GND

- 300 mV, as these ESD diodes will begin conducting current

into the substrate and affect ADC operation.

The capacitor C1 in Figure 9 typically has a value of 4 pF,

and is mainly due to pin capacitance. The resistor R1 repre-

sents the on resistance of the multiplexer and track / hold

switch, and is typically 100 ohms. The capacitor C2 is the

ADC121S101/101S101/081S101 sampling capacitor, and is

typically 26 pF.

The sampling nature of the analog input causes input current

pulses that result in voltage spikes at the input. The

ADC121S101/101S101/081S101 will deliver best perfor-

mance when driven by a low-impedance source to eliminate

distortion caused by the charging of the sampling capaci-

tance. In applications where dynamic performance is critical,

the input might need to be driven with a low output-

impedance

amplifier.

addition,

when

using

the

ADC121S101/101S101/081S101 to sample AC signals, a

band-pass or low-pass filter will reduce harmonics and noise

and thus improve THD and SNR.

6.0 DIGITAL INPUTS AND OUTPUTS

The ADC121S101/101S101/081S101 digital inputs (SCLK

and CS) are not limited by the same absolute maximum

ratings as the analog inputs. The digital input pins are in-

stead limited to +6.5V with respect to GND, regardless of

DD,

the supply voltage. This allows the ADC121S101/

101S101/081S101 to be interfaced with a wide range of logic

levels, independent of the supply voltage.

Note that, even though the digital inputs are tolerant of up to

+6.5V above GND, the digital outputs are only capable of

driving V

DD out. In addition, the digital input pins are not

prone to latch-up; SCLK and CS may be asserted before

DD without any risk.

7.0 MODES OF OPERATION

The ADC121S101/101S101/081S101 has two possible

modes of operation: normal mode, and shutdown mode. The

ADC121S101/101S101/081S101 enters normal mode (and

a conversion process is begun) when CS is pulled low. The

device will enter shutdown mode if CS is pulled high before

the tenth falling edge of SCLK after CS is pulled low, or will

stay in normal mode if CS remains low. Once in shutdown

mode, the device will stay there until CS is brought low

again. By varying the ratio of time spent in the normal and

shutdown modes, a system may trade-off throughput for

power consumption.

8.0 NORMAL MODE

The best possible throughput is obtained by leaving the

ADC121S101/101S101/081S101 in normal mode at all

times, so there are no power-up delays. To keep the device

in normal mode continuously, CS must be kept low until after

the 10th falling edge of SCLK after the start of a conversion

(remember that a conversion is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before

the 16th falling edge, the device will remain in normal mode,

but the current conversion will be aborted, and SDATA will

return to TRI-STATE (truncating the output word).

Sixteen SCLK cycles are required to read all of a conversion

word from the device. After sixteen SCLK cycles have

elapsed, CS may be idled either high or low until the next

conversion. If CS is idled low, it must be brought high again

before the start of the next conversion, which begins when

CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE.

Another conversion may be started, after t

QUIET

has

elapsed, by bringing CS low again.

20110213

FIGURE 9. Sample Circuit

20110214

FIGURE 10. Equivalent Input Circuit

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