AD7274 datasheet(7/20 Pages) AD

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REV. PrB

PRELIMINARYTECHNICALDATA

Preliminary Technical Data

AD7273/AD7274

Figure 5. AD7274 Serial Interface Timing Diagram

Timing Example 1

From Figure 6, having

fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of

t2 + 12.5(1/fSCLK) + tACQ =

333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ.

Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD

ns for tQUIET satisfying the minimum requirement of TBD ns.

Timing Example 2

Having

fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns.

With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From

Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for

tQUIET satisfying the minimum requirement of TBD ns.

Figure 6. Serial Interface Timing Example

Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.

SCLK

SDATA

2 LEADING

ZERO’S

THREE-

STATE

tquiet

tconvert

t 2

THREE-STATE

DB10

ZERO

1/ THROUGHPUT

DB11

DB9

ZERO

DB0

DB1

2 TRAILING

ZERO’S

SCLK

tquiet

tacquisition

12.5(1/fSCLK)

1/THROUGHPUT

tconvert

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