AD5253/AD5254

Rev. 0 | Page 18 of 28

Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)

A4

A3

A2

A1

A0

Data Byte Description

1

1

0

0

0

Sign and 7-Bit Integer Values of RDAC0 Tolerance (Read Only)

1

1

0

0

1

8-Bit Decimal Value of RDAC0 Tolerance (Read Only)

1

1

0

1

0

Sign and 7-Bit Integer Values of RDAC1 Tolerance (Read Only)

1

1

0

1

1

8-Bit Decimal Value of RDAC1 Tolerance (Read Only)

1

1

1

0

0

Sign and 7-Bit Integer Values of RDAC2 Tolerance (Read Only)

1

1

1

0

1

8-Bit Decimal Value of RDAC2 Tolerance (Read Only)

1

1

1

1

0

Sign and 7-Bit Integer Values of RDAC3 Tolerance (Read Only)

1

1

1

1

1

8-Bit Decimal Value of RDAC3 Tolerance (Read Only)

A

AA

D7

D6

D5

D4

D3

D2

D1

D0

SIGN

SIGN

7 BITS FOR INTEGER NUMBER

D7

D6

D5

D4

D3

D2

D1

D0

8 BITS FOR DECIMAL NUMBER

Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. Unit is %. Only Data Bytes Are Shown.

nonvolatile memory. The tolerance of each channel is stored in

the memory during the factory production and can be read by

users at any time. The knowledge of the stored tolerance, which

rheostat mode, or open-loop applications where knowledge of

absolute resistance is critical.

The stored tolerances reside in the read-only memory, and are

expressed in percent. The tolerance is coded in sign magnitude

binary, 16 bits long, and is stored in two memory locations (see

Table 10). The data format of the tolerance is the sign magni-

tude binary format; an example is shown in Figure 32. In the

first memory location of the eight data bits, the MSB is

designated for the sign (0 = + and 1= –) and the 7 LSBs are

designated for the integer portion of the tolerance. In the

second memory location, all eight data bits are designated for

the decimal portion of tolerance. As shown in Table 8 and

readback from address 11000 shows 0001 1100 and address

11001 shows 0000 1111, then RDAC0 tolerance can be

calculated as:

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

Tolerance = +28.06% and therefore

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal

order to determine if the internal write cycle is complete and

interface responds with an ACK, the write cycle is complete and

the interface is ready to proceed with further operations. Other-

Commands 2 and 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to a logic LOW after EEMEM programming

protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read

operations operate as normal. When write protection is enabled,

commands 1 (restore from EEMEM to RDAC) and 7 (reset)

function normally to allow RDAC settings to be refreshed from

the EEMEM to the RDAC registers.