REV. 0

AD1981A

–18–

CHS

Channel Select:

CHS = 0 Selects Left Channel Coefficients Data Block

CHS = 1 Selects Right Channel Coefficients Data Block

SYM

Symmetry: When set to “1,” this bit indicates that the left and right channel coefficients are equal.

This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and set up

(the right channel coefficients are fetched from the left channel memory).

MAD

Mixer ADC Loop-Back Enable: Enables mixer ADC data to be summed into PCM stream.

LBEN

0 = No Loop-Back allowed (default)

1 = Enable Loop-Back

EQM

Equalizer Mute: When set to “1,” this bit disables the equalizer function (allows all data pass-through).

The reset default sets this bit to “1,” disabling the equalizer function until the biquad coefficients can be properly set.

EQ Data Register (Index 62h)

Reg. Num. Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

62h

EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h

This read/write register is used to transfer EQ biquad coefficients into memory.

The register data is transferred to, or retrieved from, the address pointed by the BCA bits in the EQ CNTRL Register (60h). Data will only be written to memory if

the EQM Bit (Register 60h Bit 15) is asserted. DACs should be powered down when new EQ coefficients are being added.

CFD[15:0]

Coefficient Data: The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is

the MSB, and the CFD0 bit is the LSB.

Mixer ADC, Input Gain Register (Index 64h)

*For AC ‘97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit in Register 76h. The MSPLT bit enables separate

mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.

RMG[3:0]

Right Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of

+22.5 dB. The least significant bit represents 1.5 dB.

RM

Right Channel Mute: Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the IM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”

LMG[3:0]

Left Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of

+22.5 dB. The least significant bit represents 1.5 dB.

MXM

Mixer Gain Mute:

0 = Unmuted,

1 = Muted or –

∞ dB gain.

MXM

xMG3...xMG0

Function

0

1111

+22.5 dB gain

0

0000

0 dB gain

1

xxxxx

–

∞ dB gain

Jack Sense/Audio Interrupt/Status Register (Index 72h)

Reg Num Name

D15 D14 D13 D12

D11

D10

D9

D8

D7

D6

D5

D4 D3 D2

D1

D0 Default

72h

JACK SENSE

X

X

X

JS

JS

JS

JS1

JS0

JS1

JS0

JS1 JS0 JS1 JS0 JS1

JS0

0000h

MT2 MT1 MT0 EQB EQB TMR TMR MD MD ST ST INT INT

All register bits are read/write except for JS0ST and JS1ST, which are read only.

Reg Num Name

D15 D14 D13 D12

D11

D10

D9

D8

D7 D6 D5 D4

D3

D2

D1

D0

Default

64h

Mixer Volume MXM

X

X

X

LMG3 LMG2 LMG1 LMG0 RM

* X

X

X RMG3 RMG2 RMG1 RMG0 8000h