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Control Bits C3 to C0

APPLICATION INFORMATION

Stability Circuit

I

1

OUT

V

OUT

R

FB

C

1

GND

V

DD

V

DD

U1

U2

V

REF

V

REF

I

2

OUT

DAC7811

SBAS337C – APRIL 2005 – REVISED JULY 2007

Control Bits C3 to C0 allow control of various functions of the DAC; see Table 2. Default settings of the DAC on

powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.

the user to adjust certain features as part of an initialization sequence; for example, daisy-chaining may be

disabled if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to

either zero or midscale. The user may also initiate a readback of the DAC register contents for verification

purposes.

Table 2. Serial Input Register Data Format, Data Loaded MSB First

C3

C2

C1

C0

FUNCTION IMPLEMENTED

0

0

0

0

No operation (power-on default)

0

0

0

1

Load and update

0

0

1

0

Initiate readback

0

0

1

1

Reserved

0

1

0

0

Reserved

0

1

0

1

Reserved

0

1

1

0

Reserved

0

1

1

1

Reserved

1

0

0

0

Reserved

1

0

0

1

Daisy-chain disable

1

0

1

0

Clock data to shift register on rising edge

1

0

1

1

Clear DAC output to zero

1

1

0

0

Clear DAC output to midscale

1

1

0

1

Reserved

1

1

1

0

Reserved

1

1

1

1

Reserved

inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)

layout design practices. For each code change, there is a step function. If the gain bandwidth product (GBP) of

the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible.

shown in Figure 29.

Figure 29. Gain Peaking Prevention Circuit with Compensation Capacitor

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