DP83850C datasheet(19/37 Pages) NSC

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4.0 Registers (Continued)

4.7 Administration Register (ADMIN)

4.8 Device ID Register (DEVICEID)

4.9 Hub ID 0 Register (HUBID0)

Page 0

Address 4h

Bit

Bit Name

Access

Bit Description

D15 - D13 reserved

For compatibility with future enhanced versions these bits must be written as

zero. They are undeﬁned when read.

D12

TST_PART_LED

r/w

Test Partition LED: When this bit is set, the corresponding Partition LED logic

will be enabled if any of the ADMIN_DIS bits are set.

D11 - D0

ADMIN_DIS[11] ...

ADMIN_DIS[0]

r/w

Setting these bits to 0 enables the respective port (TX and RX). Writing a 1 to

any bit will disable that port. Note that port enable/disable actions will occur at

the next network idle period. For example, if an ADMIN_DIS bit is cleared dur-

ing an incoming packet, this port will only be enabled after the incoming packet

has ﬁnished. After reset, these bits default to zero (all ports enabled).

Page 0

Address 5h

Bit

Bit Name

Access

Bit Description

D15 - D13 reserved

For compatibility with future enhanced versions these bits must be written as zero.

They are undeﬁned when read.

D12

T4_PHY_DET

r/w

T4 PHY detected: This bit indicates that a T4 PHY is detected. The criteria for de-

tection of T4 PHY is that /IRD_V must be asserted approximately 5 IRD_CLKs after

the /IR_ACTIVE assertion and the SFD is also seen.

This bit remains set until reset by a register write or a reset has been applied to the

repeater.

D11 - D8

PORT_NUM

read

only

Port Number: These bits indicate the last or current receiving port number.

EE_DONE

read

only

EEPROM Access Done: This bit is set when the DP83850C has completed its read

of the EEPROM.

reserved

For compatibility with future enhanced versions these bits must be written as zero.

They are undeﬁned when read.

RID_ER

r/w

Repeater ID Error: This bit is set under two conditions:

1. When this DP83850C sees another DP83850C use the same RID number as

its own on the management bus, or,

2. RID[4:0] has been programmed with a value of 1Fh.

This bit sticks to 1 until it is cleared by a register write.

D4 - D0

RPTR_ID

r/w

Device ID: These bits are the source for the IR_VECT[4:0] pins. These bits also

supply the register address for MII serial bus accesses. At the rising edge of /RST,

the levels on RID[4:0] are latched in this register as D[4:0].

Note 1: While you can write to these bits at any time, caution must be used. First,

when a new value is entered, all subsequent accesses must be performed at this

new address. Second, if an RID number is chosen that is that is the same as anoth-

er DP83850C device, both of these devices will be rendered unreadable (there will

be contention). Recovery from this condition is only possible with a complete system

reset, since it will not be possible to write new unique RID’s to the contending

DP83850Cs.

Note 2: Since IR_VECT = 1Fh is an illegal value, D[4:0] must not be written to this

value.

Page 0

Address 6h

Bit

Bit Name

Access

Bit Description

D15 - D0 HUB_ID0[15:0]

r/w

Hub ID 0: Contains the ﬁrst 16 bits read from the EEPROM. The ﬁrst bit read will be

written to HUB_ID0[0]; the last bit read to HUB_ID0[15].

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