DP83850C datasheet(8/37 Pages) NSC

8 / 37 page

2.0 Pin Descriptions (Continued)

www.national.com

2.3 EEPROM Interface

2.4 Miscellaneous

/IR_BUS_EN

O,L

low

Inter-Repeater Bus Enable: This signal is asserted at all times (either when the

100RIC is driving the bus or receiving from the bus) and it is deasserted only when

the 100RIC switches direction from an input (receiving) mode to an output (driving)

mode. After this switch, this signal becomes asserted again.

RDIO

I/O/Z, L

—

ters. Serial protocol conforms to the IEEE 802.3u MII (Media Independent Interface)

speciﬁcation.

Note: Input buffer has a weak pull-up.

RDC

—

of this clock. RDC is limited to a maximum frequency of 2.5 MHz. At least 3 cycles

of RDC must be provided during assertion of /RST (pin 103) to ensure proper reset

of all internal blocks.

/SDV

low

Serial Data Valid: Asserted when a valid read or write command is present. Used to

detect disconnection of the management bus so that synchronization is not lost. If not

used, tie this pin to GND.

Note: Input buffer has a weak pull-up.

/ACTIVEO

O/OC, M

low

Active Out: Enable for the IR_VECT[4:0] and /IR_ACTIVE signals. Used in multi-

DP83850C systems to enable the external buffers driving these Inter Repeater Bus

signals.

A pull up of 680 1/2 must be used with this signal.

Note: A table showing pin type designation is given in section 2.5

Signal Name

Type

Active

Description

Signal Name Type Active

Pin Description

EE_CS

O, L

high

EEPROM Chip Select: Asserted during reads to EEPROM.

EE_CK

O, L

EEPROM Serial Clock: Local Clock

÷ 32 = 0.78125MHz

EE_DO

EEPROM Serial Data Out: Connected to the serial data out of the EEPROM.

EE_DI

O, L

EEPROM Serial Data In: Connected to the serial data in of the EEPROM.

Signal Name

Type

Active

Pin Description

LCK

—

Local Clock: Must be 25 MHz

± 50ppm. Used for TX data transfer to Physical Layer

devices, TX Bus data transfers and DP83850C internal state machines.

RID[4:0]

—

Repeater Identiﬁcation Number: Provides the unique vector for the IR_VECT[4:0]

signals used in Inter Repeater bus arbitration. These bit are also used to uniquely iden-

tify this chip for serial register accesses. The RID value is latched when reset is de-

asserted.

Note: The arbiter cannot use the value 1Fh as its arbitration vector. This is the

IR_VECT[4:0] bus idle state, therefore RID[4:0] must never be set to this value.

/RST

low

Reset: The chip is reset when this signal is asserted low.

GRDIO

I/O/Z, L

—

Gated Register Data Input/Output: This I/O is a gated version of RDIO. When the

“phy_access” bit in the CONFIG register is set high, the RDIO signal is passed through

to GRDIO for accessing the physical layer chips.

Note: Input buffer has a weak pull-up.

BRDC

O, L

—

Buffered Register Data Clock: Buffered version of RDC. Allows more devices to be

chained on the MII serial bus.

RDIR

O, L

high

RDIO signal.

0 = RDIO data ﬂows into the DP83850C

1 = RDIO data ﬂows out of the DP83850C

Defaults to 0 when no register access is present.

DP83850C датащи(PDF) 8 Page - National Semiconductor (TI)

DP83850C датащи(HTML) 8 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL