CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297D – AUGUST 1998 – REVISED JUNE 2002

8

POST OFFICE BOX 655303

Carry Pulse

(internal signal)

Borrow Pulse

(internal signal)

I/D CLK

I/D OUT

Figure 4. I/D OUT in Lock Condition

φB

φA2

ECPD OUT

Figure 5. Edge-Controlled Phase-Comparator Waveforms

φB

φA1

XORPD OUT

Figure 6. Exclusive-OR Phase-Detector Waveforms

tTHL

tPHL

1/F max

I/D CLK

tPHL

I/D OUT

tTLH

50% VCC

tw

1.5 V

1.5 V

50% VCC

10%

90%

3 V

0 V

VOL

≈VCC

Figure 7. Clock (ID CLK) to Output (ID OUT) Propagation Delays,

Clock Pulse Duration, and Maximum Clock-Pulse Frequency