ADS5541IPAPR datasheet(26/37 Pages) TI1

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OUTPUT INFORMATION

Differential Clock Amplitude (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

fIN = 70MHz

SNR

SFDR

INTERNAL DLL

Production Data

ADS5541

SBAS307C – MAY 2004 – REVISED FEBRUARY 2007

Bandpass filtering of the source can help produce a

of the two modes, the device enters power-down

50% duty cycle clock and reduce the effect of jitter.

mode if no clock or a slow clock is provided. The

When using a sinusoidal clock, the clock jitter further

limit of the clock frequency where the device

improves as the amplitude is increased. In that

functions properly with default settings is ensured to

sense, using a differential clock allows for the use of

be over 2MHz.

larger amplitudes without exceeding the supply rails

and absolute maximum ratings of the ADC clock

input. Figure 49 shows the performance variation of

The ADC provides 14 data outputs (D13 to D0, with

the device versus input clock amplitude. For detailed

D13 being the MSB and D0 the LSB), a data-ready

clocking

schemes

based

transformer

signal (CLKOUT, pin 43), and an out-of-range

PECL-level clocks, see the ADS5541EVM User's

indicator (OVR, pin 64) that equals '1' when the

Guide (SLWU010), available for download from

output reaches the full-scale limits.

www.ti.com.

Two different output formats (straight offset binary or

two's complement) and two different output clock

polarities (latching output data on rising or falling

edge of the output clock) can be selected by setting

DFS (pin 40) to one of four different voltages.

Table 3 details the four modes. In addition, output

enable control (OE, pin 41, active high) is provided to

put the outputs into a high-impedance state.

In the event of an input voltage overdrive, the digital

outputs go to the appropriate full-scale level. For a

positive overdrive, the output code is 0x3FFF in

straight offset binary output format, and 0x1FFF in

two's complement output format. For a negative input

overdrive, the output code is 0x0000 in straight offset

binary

output

format,

and

0x2000

two's

complement output format. These outputs to an

Figure 49. AC Performance vs Clock Amplitude

overdrive signal are ensured through design and

characterization

The output circuitry of the ADS5541, by design,

minimizes the noise produced by the data switching

In order to achieve the fastest possible sampling

transients, and, in particular, its coupling to the ADC

rates with the ADS5541, the device uses an internal

analog circuitry. Output D4 (pin 51) senses the load

delay locked loop (DLL). The effective delay range of

capacitance and adjusts the drive capability of all the

the DLL limits its use to sampling rates above

output pins of the ADC to maintain the same output

60MSPS. In order to operate the device below

slew rate described in the timing diagram of Figure 1.

60MSPS, the internal DLL must be shut off using the

Care should be taken to ensure that all output lines

DLL OFF mode described in the Serial Programming

(including CLKOUT) have nearly the same load as

Interface section. The Typical Characteristics show

D4 (pin 51). This circuit also reduces the sensitivity

the

performance

obtained

both

modes

of the output timing versus supply voltage or

operation: DLL ON (default) and DLL OFF. In either

temperature. Placing external resistors in series with

the outputs is not recommended.

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