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ADS5541IPAPR датащи(PDF) 24 Page - Texas Instruments

номер детали ADS5541IPAPR
подробное описание детали  14-Bit, 105MSPS Analog-To-Digital Converter
PDF  37 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5541IPAPR датащи(HTML) 24 Page - Texas Instruments

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R
F
R
G
V
OCM
INP
INM
CM
R
F
R
G
R
S
0.1
µF
0.1
µF
10
µF
1
µF
R
T
+3.3V
+5V
0.1
µF
10
µF
−5V
THS4503
R
IN
R
IN
10
ADS5541
14-Bit / 105MSPS
POWER-SUPPLY SEQUENCE
REFERENCE CIRCUIT
AVDD
REFP
29
28
2k
1
1
µF
POWER-DOWN
29
30
31
R EF P
R EF M
IR EF
1
1
56k
1
µF
1
µF
Production Data
ADS5541
SBAS307C – MAY 2004 – REVISED FEBRUARY 2007
Figure 42. Using the THS4503 with the ADS5520
Using the serial interface PDN bit to power down the
device places the outputs in a high-impedance state
and only the internal reference remains on to reduce
The preferred mode of power-supply sequencing is
the power-up time. The power-down mode reduces
to power up AVDD first, followed by DRVDD. Raising
power dissipation to approximately 180mW.
both
supplies
simultaneously
is
also
a
valid
power-supply sequence. In the event that DRVDD
powers up before AVDD in the system, AVDD must
power up within 10ms of DRVDD. Optionally, it is
The
ADS5541
has
built-in
internal
reference
recommended to put a 2k
Ω resistor from REFP (pin
generation, requiring no external circuitry on the
29)
to
AVDD as shown in Figure 43. This
printed
circuit
board
(PCB).
For
optimum
configuration helps to make the device more robust
performance, it is best to connect both REFP and
to power supply ramp-up timings.
REFM to ground with a 1
µF decoupling capacitor
(the 1
Ω resistor shown in Figure 44 is optional). In
addition, an
external
56k
Ω resistor should be
connected from IREF (pin 31) to AGND to set the
proper current for the operation of the ADC, as
shown in Figure 44. No capacitor should
be
connected between pin 31 and ground; only the
56k
Ω resistor should be used.
Figure 43.
The device enters power-down in one of two ways:
either by reducing the clock speed or by setting the
PDN bit via the serial programming interface. Using
the reduced clock speed, power-down may be
initiated for clock frequency below 2MSPS. The
exact frequency at which the power-down occurs
varies from device to device.
Figure 44. REFP, REFM, and IREF Connections
for Optimum Performance
24
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