PCI9080 datasheet(26/192 Pages) ETC

26 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 17

Version 1.02

3.4.1 PCI Bus Access to Internal Registers

PCI 9080 “PCI configuration registers” can be accessed

from the PCI bus with a configuration Type 0 cycle.

PCI 9080 internal registers can be accessed by a

memory cycle, with the PCI bus address that matches

the base address specified in the PCI Base Address 0

for Memory Mapped Configuration Register of PCI 9080.

They can also be accessed by an I/O cycle, with the PCI

bus address matching the base address specified in the

PCI Base Address 1 for I/O Mapped Configuration

All PCI read or write accesses to the PCI 9080 registers

can be byte, word, or Lword accesses. All PCI memory

accesses to the PCI 9080 registers can be burst or non-

burst. PCI 9080 responds with a PCI Disconnect for all

burst I/O accesses to PCI 9080 registers.

3.4.2 Local Bus Access to Internal

Registers

The local processor can access all the internal registers

of the PCI 9080 through either internal or external

address decode logic. PCI 9080 provides an Address

Decode Mode Pin (ADMODE) that selects whether the

internal address decode logic is used or whether the

designer will supply an external chip select from an

external address decoder. Figure 3-3 illustrates how the

dual address decode logic works.

If the Address Decode Mode pin is set to 1, internal PCI

9080 address decode logic is enabled. In this mode, PCI

9080 internal registers are selected when local address

bits LA[31:29] match input address select pins S[2:0]. If

the Address Decode Mode pin is set to 0, PCI 9080

responds to local bus access when S0 is asserted low

through external chip select logic.

Notes: S0 must be decoded while ADS# is low.

If ADMODE is 1 LA[31:29], specify 512 MB of

local memory space allocated for accessing internal

registers.

All local read or write accesses to the PCI 9080 registers

can be byte, word, or Lword accesses. All local

accesses to the PCI 9080 registers can be burst or non-

burst.

For C and J modes, accesses must be for a 32 bit

nonpipelined bus. PCI 9080 READYo# indicates a data

transfer is complete.

For S mode, accesses must be for a 16 bit nonpipelined

bus. PCI 9080 READYo# indicates a data transfer is

complete.

Figure 3-3. Dual Address Decode Mode

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