PCI9080 datasheet(21/192 Pages) ETC

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 12

Version 1.02

3. FUNCTIONAL DESCRIPTION

Functional operation described can be changed or

modified, depending on the register configuration.

3.1 RESET

3.1.1 PCI Bus Input RST#

PCI bus RST# input pin is a PCI host reset. It causes all

PCI bus outputs to float, resets the entire PCI 9080 and

causes the local reset output, LRESETo#, to be

asserted. If you have a PCI host, Table 4-11[2:0] (Master

Enable, Memory Space, I/O Space) is programmed by

the host after initialization is complete (Table 4-

59[31]=1). (Refer to Figure 3-1.)

!"#$

% &

Figure 3-1. Reset and Initialization Process

3.1.2 Software Reset LRESETo#

When asserted, the LRESETo# Software Reset bit

(Table 4-59[30]) resets PCI 9080 Local Configuration

and Local DMA Registers. However, it does not reset the

PCI Configuration and Shared Runtime Registers. When

the bit is set, PCI 9080 responds to PCI accesses, but

not to local accesses. PCI 9080 remains in this condition

until PCI host clears the bit. The serial EEPROM is

reloaded if Table 4-59[29] is set.

3.1.3 Local Bus Input LRESETi#

When asserted, the LRESETi# input resets the local bus

portion of PCI 9080, clears all local configuration and

DMA registers and causes LRESETo# output to be

asserted.

3.1.4 Local Bus Output LRESETo#

LRESETo# is asserted when PCI bus RST# input is

asserted, the LRESETi# input is asserted, or the

software reset bit in the Init Control Register is set to 1.

3.1.5 Software Reset

A host on the PCI bus can set the software reset bit in

the Init Control Register to reset PCI 9080 and assert the

LRESETo# output. All local configuration and DMA

registers reset. PCI configuration registers do not reset.

When the software reset bit is set, PCI 9080 responds to

PCI accesses, but not to local bus accesses. PCI 9080

remains in this reset condition until the PCI host clears

the bit.

Note:

The local side cannot clear this reset bit

because the local bus is in a reset state.

3.2 PCI 9080 INITIALIZATION

PCI 9080 configuration registers can be programmed by

an optional serial EEPROM and/or by a local processor,

as listed in Table 3-1. The serial EEPROM can be

reloaded by setting bit 29 of

(LOC:ECh), Serial

EEPROM Control Register (refer to Table 4-59[29]).

In general, PCI 9080 retries all PCI cycles until the

“Local Init Done bit” is set or NB# is low.

Note:

Internal configuration register can also be

accessed by the PCI host processor after power-on.

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