October 2001

7

MICRF005

MICRF005

Micrel

DO Pin

VDDBB

VSSBB

Compa-

rator

80

µA

80

µA

DO

Figure 4. DO Pin

The output stage for DO (digital output) is shown in Figure 4.

The output is a 90

µA push and 90µA pull switched-current

stage. This output stage is capable of driving CMOS loads.

An external buffer-driver is recommended for driving high-

capacitance loads.

REFOSC Pin

250

Ω

200k

Active

Bias

REFOSC

15pF

7.5pF

30

µA

VDDBB

VSSBB

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input imped-

ance is high (300k

Ω). This is a Colpitts oscillator with internal

capacitors. The nominal dc bias voltage on this pin is 1.4V.

SHUT Pin

to Internal

Circuits

VDDBB

VSSBB

SHUT

Q2

Q3

Q1

VSSBB

Figure 6. SHUT Pin

Control input circuitry is shown in Figures 6. The standard

input is a logic inverter constructed with minimum geometry

MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large

channel length device which functions essentially as a “weak”

pullup to V

impedance to the V

T/R Pin

VSSBB

Q2

VDDBB

VDDBB

Q1

Q3

Figure 7. T/R Pin

The transmit/receive function is controlled by the logic state

of T/R. T/R is internally tied to V

or in the low state, the MICRF005 functions in its normal

receive operating mode. The T/R pin may be pulled high to

Vdd, this will place the receiver in a “stand-by” operating

mode. This mode is intended for use during transmit cycles

in transceiver applications where the receiver is co-located

with a transmitter. In this “transmit” mode, the receiver

oscillator remains active but the AGC function is disabled and

the C

This function enables the MICRF005 to quickly resume

receive operation after a transmit cycle.