TAS3103DBT datasheet(46/146 Pages) TI

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2−14

2.2

DPLL and Clock Management

Clock management for the TAS3103 consists of two control structures:

•

Master clock management: oversees the selection of the clock frequencies for the microprocessor, the I2C

controller, and the digital audio processor (DAP). The master clock (MCLKI or XTALI) serves as the source

for these clocks. In most applications, the master clock is input to an on-chip digital phase lock loop (DPLL),

and the DPLL output is used to drive the microprocessor and DAP clocks. A DPLL bypass mode can also

be used, in which case the master clock is used to drive the microprocessor and DAP clocks.

•

Serial audio port (SAP) clock management: oversees SAP master/slave mode, the settings of SCLKOUT1

and SCLKOUT2, and the setting of LRCLK in the SAP master mode.

Figure 2−14 illustrates the clock circuitry in the TAS3103. The bold lines in Figure 2−14 highlight the default settings

at power turn on, or after a reset. Inputs MCLKI and XTALI source the master clock for the TAS3103. Within the

TAS3103, these two inputs are combined by an OR gate, and thus only one of these two sources can be active at

any one time. The source that is not active must be set to logic 0. In normal operation, the master clock is divided

by 1, 2, or 4 (as determined by the logic levels set at input pins PLL0 and PLL1) and then multiplied by 11 in frequency

by the on-chip DPLL. The DPLL output (or MCLKI/XTALI if the DPLL is bypassed) is the processing clock used by

the digital audio processor (DAP).

The DAP processing clock can also serve as the clock for the on-chip microprocessor, or the DAP clock can be divided

by four prior to sending it to the microprocessor. The input pin MICROCLK_DIV makes this clock choice. A logic 1

input level on this pin selects the DAP clock for the microprocessor clock; a logic 0 input level on this pin selects the

DAP clock/four for the microprocessor clock.

The selected microprocessor clock is also used to drive the clocks used by the I2C control block. Two parameters,

N and M, define the clocks used by the I2C control block. The I2C control block sampling frequency is set by 1/2N,

where N can range in value from 0 to 7. A 1/(1 + M) divisor followed by a 1/10 divisor generates the data bit clock

(SCL). This drived SCL clock is only used when the I2C control block is set to master mode (input pin I2CM_S = 1).

The default value for the I2C parameter N depends on whether the I2C controller is in a slave mode (I2CM_S = 0)

or a master mode (I2CM_S = 1). In the I2C master mode N = 2 (2N = 4), which assures that a 100-kHz I2C data clock

(SCL) can be generated when the digital audio processor (DAP) is running at its maximum frequency of 135 MHz.

In the I2C slave mode N = 1 (2N = 2), which assures the I2C controller an adequate over-sampling clock when the

DAP is running at the minimum clock frequency required to process 8-kHz audio data (approximately 11.2 MHz). In

I2C master mode, the values for M and N are fixed and cannot be changed.

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