TAS3103DBT datasheet(42/146 Pages) TI

42 / 146 page

2−10

ORIN

TAS3103

SDOUT1

ORIN

TAS3103

SDOUT1

(AB = ’1’)

(AB = ’0’)

UU2

LRCLK

SDOUT1U1

LRCLK

UU1

VU2

WU2

XU2

VU1

WU1

XU1

Figure 2−10. 8 CH TDM Format Using SAP Modes 0101 and 1000

ORIN

TAS3103

SDOUT1

ORIN

TAS3103

SDOUT1

(AB = 0)

(AB = 1)

UU1

LRCLK

SDOUT1U1

LRCLK

UU2

VU1

WU1

YU2

WU2

Figure 2−11. 6 CH Data, 8 CH Transfer TDM Format Using SAP Modes 0101 and 1000

For these same two modes, if register X in chip AB = 0 is set to zero, and registers V and X in chip AB = 1 are set

to zero, the resulting format is a 6 CH data, 8 CH transfer format. This option is shown in Figure 2−11.

The data output format in Figure 2−11 is identical to that realized using data output formats 1100 and 1110 in

Figure 2−7. The difference is that SAP modes 1010 and 1000 provide six independent monaural channels to process

the data, whereas SAP modes 1100 and 1110 provide only three independent monaural channels to process the data.

2.1.2

Processing Flow—SAP Input to SAP Output

All SAP data format options other than I2S result in a two-sample delay from input to output, as illustrated in

Figure 2−12. Figure 2−12 is also relevant if I2S formatting is used for both the input SAP and the output SAP (the

polarity of LRCLK in Figure 2−12 has to be inverted in this case). However, if I2S format conversions are performed

between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock

frequency selected for the digital audio processor (DAP) relative to the sample rate of the incoming data. The input

to output delay for an I2S input format and a non-I2S output format is illustrated in Figure 2−13(a), and Figure 2−13(b)

illustrates the delay for a non-I2S input format and an I2S output format. In each case, two distinct input to output delay

times are shown: a 1.5 sample delay time if the processing time in the DAP is less than half the sample period, and

a 2.5 sample delay time if the processing time in the DAP is greater than half the sample period.

The departure from the two-sample input to output processing delay when I2S format conversions are performed is

due to the use of a common LRCLK. The I2S format uses the falling edge of LRCLK to begin a sample period, whereas

all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and digital

audio processor (DAP) operate on sample windows that are 180

° out of phase with respect to the sample window

used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint

of the sample period used by the DAP to process the data. If the processing cycle completes all processing tasks

before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the

processing time extends past the midpoint of the processing sample period, the output SAP outputs the data

processed during the previous processing sample period. In the former case, the delay from input to output is 1.5

samples. In the latter case, the delay from input to output is 2.5 samples.

TAS3103DBT датащи(PDF) 42 Page - Texas Instruments

TAS3103DBT датащи(HTML) 42 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL