Output Interface — Control Outputs

PCLK (Parallel Clock): The parallel output or word clock,

PCLK, is synchronous with the parallel data outputs, PD0–9.

The rising edge of PCLK is located at the center of the par-

allel data window.

TRS (Timing Reference Signal): The active-low TRS out-

put pulse is four parallel clock periods long. TRS is active

during decoding of both composite and component video

signals.

EAV (End of Active Video): The EAV output is pulsed low

for one cycle of the parallel clock every time an EAV timing

reference is detected during decoding of component video.

The pulse is coincident with the fourth word of the timing ref-

erence (the XYZ word). During reception of composite video,

this output is always asserted high.

NSP (New Sync Position): The active-low NSP output indi-

cates that the most recently received TRS is in a different po-

sition relative to the previous TRS. NSP remains high until

the parallel rate clock is properly aligned with the TRS, then

goes low.

PCB Layout Guidelines

The CLC011 is not as sensitive to PCB layout as some Serial

Digital Video decoders. The following suggestions will help

achieve and maintain optimum system performance.

1.

Locate the CLC011 decoder away from equalizers and

other sensitive circuitry to avoid unwanted crosstalk from

clock and data outputs which may degrade system per-

formance.

2.

The trace from the signal input connector to the CLC011

must be kept short and should not run parallel to the

data output traces.

3.

Bypass each power pin with a 0.01 µF to 0.1 µF mono-

lithic ceramic capacitor.

4.

Power the CLC011 and other clock recovery circuitry

from a separate power supply network from that of other

digital circuitry on the board.

Other PCB layout tips may be found in: “Keeping Analog Sig-

nals Pure in a Hostile Digital World”, Electronic Design, Spe-

cial Analog Issue, June 24, 1996, available from National

Semiconductor. Request Literature number 665502-001.

www.national.com

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