Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: Nominal position of rising edge of serial clock is at the center of the serial data eye.

Note 4: Nominal position of the rising edge of PCLK is at the center of the PDn eye.

Note 5: See Timing Diagrams.

Note 6: Data latency due to digital registers, measured from MSB of serial data to parallel clock out.

Note 7: Total latency is the digital latency plus the output buffer latency.

Note 8: 100% tested at 25˚C, sample tested over temperature.

Note 9: Typicals only specified.

Timing Diagrams

DS100086-3

FIGURE 1.

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