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AD9684 датащи(PDF) 9 Page - Analog Devices

номер детали AD9684
подробное описание детали  Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter
PDF  64 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9684 датащи(HTML) 9 Page - Analog Devices

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Product
Overview
Online
Documentation
Design
Resources
Discussion
Sample
& Buy
Data Sheet
AD9684
Rev. 0 | Page 9 of 64
D13
D0
D13
D0
CLK+
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST1
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST2
SYNC+
APERTURE DELAY
N
N + x
N – 1
N + y
N + 35
N + 36
N + 37
N + 38
SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
D0±
D13±
FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
CONVERTER 0
SAMPLE
[N]
N + 39
N + 40
N + 41
VIN±x
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
STATUS
STATUS
D13
D0
STATUS
D13
D0
STATUS
D13
D0
STATUS
D13
D0
STATUS
D13
D0
STATUS
CLK–
SYNC–
STATUS+
(OVERRANGE/STATUS BIT)
STATUS–
tCLK
tDCO
tPD
tSKEWR
CONVERTER 0
SAMPLE
[N + 1]
CONVERTER 0
SAMPLE
[N + 2]
CONVERTER 0
SAMPLE
[N + 3]
CONVERTER 0
SAMPLE
[N + 4]
tSKEWF
CONSTANT LATENCY = X CLK CYCLES
Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data



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