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AD9680

Data Sheet

Rev. C | Page 66 of 97

The SYNCINB± pin operation can also be controlled by the

SPI. The SYNCINB± signal is a differential dc-coupled LVDS

mode signal by default, but it can also be driven single-ended.

For more information on configuring the SYNCINB± pin

operation, refer to Register 0x572.

The SYNCINB± pins can also be configured to run in CMOS

(single-ended) mode, by setting Bit[4] in Register 0x572. When

running SYNCINB± in CMOS mode, connect the CMOS

SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20

(SYNCINB−) floating.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with

an /R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe, the link configuration data is sent, starting

with the third character. The second character is a /Q/ character

to confirm that the link configuration data will follow. All

undefined data slots are filled with ramp data. The ILAS

sequence is never scrambled.

The ILAS sequence construction is shown in Figure 158. The

four multiframes include the following:

•

Multiframe 1. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 2. Begins with an /R/ character followed by a

/Q/ character (/K28.4/), followed by link configuration

parameters over 14 configuration octets (see Table 24) and

ends with an /A/ character. Many of the parameter values

are of the value – 1 notation.

•

Multiframe 3. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

•

Multiframe 4. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

User Data and Error Detection

After the initial lane alignment sequence is complete, the user

data is sent. Normally, within a frame, all characters are considered

user data. However, to monitor the frame clock and multiframe

clock synchronization, there is a mechanism for replacing

characters with /F/ or /A/ alignment characters when the data

meets certain conditions. These conditions are different for

unscrambled and scrambled data. The scrambling operation is

enabled by default, but it can be disabled using the SPI.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a

multiframe is replaced with an /A/. The JESD204B receiver (Rx)

checks for /F/ and /A/ characters in the received data stream

and verifies that they only occur in the expected locations. If an

unexpected /F/ or /A/ character is found, the receiver handles

the situation by using dynamic realignment or asserting the

SYNCINB± signal for more than four frames to initiate a

resynchronization. For unscrambled data, if the final character

of two subsequent frames is equal, the second character is

replaced with an /F/ if it is at the end of a frame, and an /A/ if

it is at the end of a multiframe.

Insertion of alignment characters can be modified using SPI.

The frame alignment character insertion (FACI) is enabled by

default. More information on the link controls is available in the

Memory Map section, Register 0x571.

8-Bit/10-Bit Encoder

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed.

The control characters used in JESD204B are shown in Table 24.

The 8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

The 8-bit/10-bit interface has options that can be controlled via

the SPI. These operations include bypass and invert. These options

are troubleshooting tools for the verification of the digital front

end (DFE). See the Memory Map section, Register 0x572[2:1]

for information on configuring the 8-bit/10-bit encoder.

START OF

ILAS

START OF LINK

CONFIGURATION DATA

END OF

MULTIFRAME

START OF

USER DATA

Figure 158. Initial Lane Alignment Sequence

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