Micro Crystal

Real Time Clock / Calendar Module

RV-8564

23/40

10.CHARACTERISTICS OF THE I

The I

Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up

resistors. Data transfer may be initiated only when the bus is not busy.

10.1.BIT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH

period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data

changes should be executed during the LOW period of the clock pulse.

10.2.START AND STOP CONDITIONS

Both SDA data and SCL clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP condition (P).