MB9B520M datasheet(83/113 Pages) SPANSION

83 / 113 page

D a t a S h e e t

MB9B520M_DS706-00048-3v0-E, March 18, 2015

CONFIDENTIAL

(11) I

2C Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)

Parameter

Symbol

Conditions

Standard-

mode

Fast-

mode

Unit Remarks

Min

Max

Min

Max

SCL clock frequency

fSCL

CL = 30 pF,

R = (VP/IOL)*

100

400 kHz

(Repeated) START condition

hold time

SDA ↓ → SCL ↓

tHDSTA

4.0

0.6

μs

SCL clock L width

tLOW

4.7

1.3

μs

SCL clock H width

tHIGH

4.0

0.6

μs

(Repeated) START condition

setup time

SCL ↑ → SDA ↓

tSUSTA

4.7

0.6

μs

Data hold time

SCL ↓ → SDA ↓ ↑

tHDDAT

3.45*

0.9*

μs

Data setup time

SDA ↓ ↑ → SCL ↑

tSUDAT

250

100

STOP condition setup time

SCL ↑ → SDA ↑

tSUSTO

4.0

0.6

μs

Bus free time between

STOP condition and

START condition

tBUF

4.7

1.3

μs

Noise filter

tSP

2 tCYCP*

*1:R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.

VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.

*2:The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.

*3:A Fast mode I

2C bus device can be used on a Standard mode I2C bus system as long as the device

satisfies the requirement of "tSUDAT ≥ 250 ns".

*4:tCYCP is the APB bus clock cycle time.

About the APB bus number that I

2C is connected to, see "Block Diagram" in this data sheet.

To use Standard-mode, set the APB bus clock at 2 MHz or more

To use Fast-mode, set the APB bus clock at 8 MHz or more.

SDA

SCL

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