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ADC12441CMJ датащи(PDF) 12 Page - National Semiconductor (TI) |
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ADC12441CMJ датащи(HTML) 12 Page - National Semiconductor (TI) |
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12 / 14 page ![]() 30 Analog Considerations (Continued) For absolute accuracy where the analog input varies be- tween very specific voltage limits the reference pin can be biased with a time and temperature stable voltage source In general the magnitude of the reference voltage will re- quire an initial adjustment to null out full-scale errors 32 INPUT CURRENT Because the input network of the ADC12441 is made up of a switch and a network of capacitors a charging current will flow into or out of (depending on the input voltage polarity) of the analog input pin (VIN) on the start of the analog input sampling period (tA) The peak value of this current will de- pend on the actual input voltage applied 33 NOISE The leads to the analog input pin should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to this input can cause er- rors Input filtering can be used to reduce the effects of these noise sources 34 INPUT BYPASS CAPACITORS An external capacitor can be used to filter out any noise due to inductive pickup by a long input lead and will not degrade the accuracy of the conversion result 35 INPUT SOURCE RESISTANCE The analog input can be modeled as shown in Figure 3 External RS will lengthen the time period necessary for the voltage on CREF to settle to within LSB of the analog input voltage With fCLK e 2 MHz tA e 7 clock periods e 35 ms RS s 1kX will allow a 5V analog input voltage to settle properly 36 POWER SUPPLIES Noise spikes on the VCC and V b supply lines can cause conversion errors as the comparator will respond to this noise The AD is especially sensitive during the auto-zero or auto-cal procedures to any power supply spikes Low in ductance tantalum capacitors of 10 mF or greater paralleled with 01 mF ceramic capacitors are recommended for supply bypassing Separate bypass capacitors whould be placed close to the DVCC AVCC and V b pins If an unregulated voltage source is available in the system a separate LM340LAZ-50 voltage regulator for the A-to-D’s VCC (and other analog circuitry) will greatly reduce digital noise on the supply line 37 THE CALIBRATION CYCLE On power up the ADC12441 goes through an Auto-Cal cy- cle which cannot be interrupted Since the power supply reference and clock will not be stable at power up this first calibration cycle will not result in an accurate calibration of the AD A new calibration cycle needs to be started after the power supplies reference and clock have been given enough time to stabilize During the calibration cycle cor- rection values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full scale offset and linearity errors down to the specified limits Full scale error typically changes g01 LSB over temperature and linearity error changes even less therefore it should be necessary to go through the calibration cycle only once af- ter power up if auto-zero is used to correct the zero error change 38 THE AUTO-ZERO CYCLE To correct for any change in the zero (offset) error of the AD the auto-zero cycle can be used It may be necessary to do an auto-zero cycle whenever the ambient temperature changes significantly (See the curved titled ‘‘Zero Error Change vs Ambient Temperature’’ in the Typical Perform- ance Characteristics) A change in the ambient temperature will cause the VOS of the sampled data comparator to change which may cause the zero error of the AD to be greater than g1 LSB An auto-zero cycle will maintain the zero error to g1 LSB or less TLH11017 – 21 FIGURE 3 Analog Input Equivalent Circuit 12 |
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