ADC12441CMJ datasheet(10/14 Pages) NSC

10 / 14 page

10 Pin Descriptions

DVCC (28)

The digital and analog positive power supply

AVCC (4)

pins The digital and analog power supply

voltage range of the ADC12441 is a45V to

55V To guarantee accuracy it is required

that the AVCC and DVCC be connected to-

gether to the same power supply with sepa-

rate bypass filters (10 mF tantalum in parallel

with a 01 mF ceramic) at each VCC pin

(5)

The analog negative supply voltage pin Vb

has a range of b45V to b55V and needs a

bypass filter of 10 mF tantalum in parallel with

a 01 mF ceramic

DGND (14)

The digital and analog ground pins AGND

AGND (3)

and DGND must be connected together ex-

ternally to guarantee accuracy

VREF (2)

The reference input voltage pin To maintain

accuracy the voltage at this pin should not

exceed the AVCC or DVCC by more than

50 mV or go below 35 VDC

VIN (1)

The analog input voltage pin To guarantee

accuracy the voltage at this pin should not

exceed VCC by more than 50 mV or go below

Vb by more than 50 mV

CS (10)

The Chip Select control input This input is

active low and enables the WR and RD func-

tions

RD (11)

The Read control input With both CS and RD

low the TRI-STATE output buffers are en-

abled and the INT output is reset high

WR (7)

The Write control input The converison is

started on the rising edge of the WR pulse

when CS is low

CLK (8)

The external clock input pin The clock fre-

quency range is 500 kHz to 4 MHz

CAL (9)

The Auto-Calibration control input

When

CAL is low the ADC12441 is reset and a cali-

bration cycle is initiated During the calibra-

tion cycle the values of the comparator offset

voltage and the mismatch errors in the ca-

pacitor reference ladder are determined and

stored in RAM These values are used to cor-

rect the errors during a normal cycle of AD

conversion

AZ (6)

The Auto-Zero control input With the AZ pin

held low during a conversion the ADC12441

goes into an auto-zero cycle before the actu-

al AD conversion is started This Auto-Zero

cycle corrects for the comparator offset volt-

age The total conversion time (tC)isin-

creased by 26 clock periods when Auto-Zero

is used

EOC (12)

The End-of-Conversion control output This

output is low during a conversion or a calibra-

tion cycle

INT (13)

The Interrupt control output This output goes

low when a conversion has been completed

and indicates that the conversion result is

available in the output latches Reading the

result or starting a conversion or calibration

cycle will reset this output high

DB0 – DB12

The TRI-STATE output pins The output is in

(15 – 27)

two’s complement format with DB12 the sign

bit DB11 the MSB and DB0 the LSB

20 Functional Description

The ADC12441 is a 12-bit plus sign AD converter with the

capability of doing Auto-Zero or Auto-Cal routines to mini-

mize zero full-scale and linearity errors It is a successive-

approximation AD converter consisting of a DAC compar-

ator and a successive-approximation register (SAR) Auto-

Zero is an internal calibration sequence that corrects for the

AD’s zero error caused by the comparator’s offset voltage

Auto-Cal is a calibration cycle that not only corrects zero

error but also corrects for full-scale and linearity errors

caused by DAC inaccuracies Auto-Cal minimizes the errors

of the ADC12441 without the need of trimming during its

fabrication An Auto-Cal cycle can restore the accuracy of

the ADC12441 at any time which ensures its long term sta-

bility

21 DIGITAL INTERFACE

On power up a calibration sequence should be initiated by

pulsing CAL low with CS RD and WR high To acknowl-

edge the CAL signal EOC goes low after the falling edge of

CAL and remains low during the calibration cycle of 1396

clock periods During the calibration sequence first the

comparator’s offset is determined

then the capacitive

DAC’s mismatch error is found Correction factors for these

errors are then stored in internal RAM

A conversion is initiated by taking CS and WR low The AZ

(Auto Zero) signal line should be tied high or low during the

conversion process If AZ is low an auto zero cycle which

takes approximately 26 clock periods occurs before the ac-

tual conversion is started The auto zero cycle determines

the correction factors for the comparator’s offset voltage If

AZ is high the auto zero cycle is skipped Next the analog

input is sampled for 7 clock periods and held in the capaci-

tive DAC’s ladder structure The EOC then goes low signal-

ing that the analog input is no longer being sampled and

that the AD successive approximation conversion has

started

During a conversion the sampled input voltage is succes-

sively compared to the output of the DAC First the ac-

quired input voltage is compared to analog ground to deter-

mine its polarity The sign bit is set low for positive input

voltages and high for negative Next the MSB of the DAC is

set high with the rest of the bits low If the input voltage is

greater than the output of the DAC then the MSB is left

high otherwise it is set low The next bit is set high making

the output of the DAC three quarters or one quarter of full

scale A comparison is done and if the input is greater than

the new DAC value this bit remains high if the input is less

than the new DAC value the bit is set low This process

continues until each bit has been tested The result is then

stored in the output latch of the ADC12441 Next EOC goes

high and INT goes low to signal the end of the conversion

The result can now be read by taking CS and RD low to

enable the DB0 – DB12 output buffers

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