ADC08231CIWM datasheet(17/24 Pages) NSC

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Functional Description (Continued)

40 THE ANALOG INPUTS

The most important feature of these converters is that they

can be located right at the analog signal source and through

just a few wires can communicate with a controlling proces-

sor with a highly noise immune serial bit stream This in itself

greatly minimizes circuitry to maintain analog signal accura-

cy which otherwise is most susceptible to noise pickup

However a few words are in order with regard to the analog

inputs should the input be noisy to begin with or possibly

riding on a large common-mode voltage

The differential input of these converters actually reduces

the effects of common-mode input noise a signal common

to both selected ‘‘a’’ and ‘‘b’’ inputs for a conversion

(60 Hz is most typical) The time interval between sampling

the ‘‘a’’ input and then the ‘‘b’’ input is

of a clock peri-

od The change in the common-mode voltage during this

short time interval can cause conversion errors For a sinus-

oidal common-mode signal this error is

Verror(max) e VPEAK(2qfCM)

fCLK

where fCM is the frequency of the common-mode signal

VPEAK is its peak voltage value

and fCLK is the AD clock frequency

For a 60Hz common-mode signal to generate a

LSB er-

ror (

5mV) with the converter running at 250kHz its peak

value would have to be 663V which would be larger than

allowed as it exceeds the maximum analog input limits

Source resistance limitation is important with regard to the

DC leakage currents of the input multiplexer While operat-

ing near or at maximum speed bypass capacitors should

not be used if the source resistance is greater than 1kX

The worst-case leakage current of g1mA over temperature

will create a 1mV input error with a 1kX source resistance

An op amp RC active low pass filter can provide both im-

pedance buffering and noise filtering should a high imped-

ance signal source be required

50 OPTIONAL ADJUSTMENTS

51 Zero Error

The zero of the AD does not require adjustment If the

minimum analog input voltage value VIN(MIN) is not ground

a zero offset can be done The converter can be made to

output 0000 0000 digital code for this minimum input voltage

by biasing any VIN (b) input at this VIN(MIN) value This

utilizes the differential mode operation of the AD

The zero error of the AD converter relates to the location

of the first riser of the transfer function and can be mea-

sured by grounding the VIN (b) input and applying a small

magnitude positive voltage to the VIN (a) input Zero error

is the difference between the actual DC input voltage which

is necessary to just cause an output digital code transition

from 0000 0000 to 0000 0001 and the ideal

LSB value

(

LSB e 98mV for VREF e 5000VDC)

52 Full Scale

A full-scale adjustment can be made by applying a differen-

tial input voltage which is 1

LSB down from the desired

analog full-scale voltage range and then adjusting the mag-

nitude of the VREFIN input for a digital output code which is

just changing from 1111 1110 to 1111 1111 (See figure enti-

tled ‘‘Span Adjust 0V s VIN s 3V’’) This is possible only

with the ADC08234 and ADC08238 (The reference is inter-

nally connected to VREFIN of the ADC08231)

53 Adjusting for an Arbitrary Analog Input

Voltage Range

If the analog zero voltage of the AD is shifted away from

ground (for example to accommodate an analog input sig-

nal which does not go to ground) this new zero reference

should be properly adjusted first A VIN (a) voltage which

equals this desired zero reference plus

LSB (where the

LSB is calculated for the desired analog span using 1 LSB

analog span256) is applied to selected ‘‘a’’ input and

the zero reference voltage at the corresponding ‘‘b’’ input

should then be adjusted to just obtain the 00HEX to 01HEX

code transition

The full-scale adjustment should be made with the proper

VIN (b) voltage applied by forcing a voltage to the VIN (a)

input which is given by

VIN (a)fsadj e VMAX b 15

(VMAX b VMIN)

256

(

where

VMAX e the high end of the analog input range

and

VMIN e the low end (the offset zero) of the analog range

(Both are ground referenced)

The VREFIN (or VCC) voltage is then adjusted to provide a

code change from FEHEX to FFHEX This completes the ad-

justment procedure

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