ADC08231CIWM datasheet(16/24 Pages) NSC

16 / 24 page

Functional Description (Continued)

3 When the start bit has been shifted into the start location

of the MUX register the input channel has been assigned

and a conversion is about to begin An interval of 1

clock periods is automatically inserted to allow for sam-

pling the analog input The SARS line goes high at the

end of this time to signal that a conversion is now in prog-

ress and the DI line is disabled (it no longer accepts

data)

4 The data out (DO) line now comes out of TRI-STATE and

provides a leading zero

5 During the conversion the output of the SAR comparator

indicates whether the analog input is greater than (high)

or less than (low) a series of successive voltages gener-

ated internally from a ratioed capacitor array (first 5 bits)

and a resistor ladder (last 3 bits) After each comparison

the comparator’s output is shipped to the DO line on the

falling edge of CLK This data is the result of the conver-

sion being shifted out (with the MSB first) and can be

read by the processor immediately

6 After 8 clock periods the conversion is completed The

SARS line returns low to indicate this

clock cycle later

7 The stored data in the successive approximation register

is loaded into an internal shift register If the programmer

prefers the data can be provided in an LSB first format

this makes use of the shift enable (SE) control line

the ADC08238 the SE line is brought out and if held high

the value of the LSB remains valid on the DO line When

SE is forced low the data is clocked out LSB first On

devices which do not include the SE control line the

data LSB first is automatically shifted out the DO line

after the MSB first data stream The DO line then goes

low and stays low until CS is returned high

The

ADC08231 is an exception in that its data is only output in

MSB first format

8 All internal registers are cleared when the CS line is high

and the tSELECT requirement is met See Data Input Tim-

ing under Timing Diagrams If another conversion is de-

sired CS must make a high to low transition followed by

address information

The DI and DO lines can be tied together and controlled

through a bidirectional processor IO bit with one wire

This is possible because the DI input is only ‘‘looked-at’’

during the MUX addressing interval while the DO line is

still in a high impedance state

30 REFERENCE CONSIDERATIONS

The VREFIN pin on these converters is the top of a resistor

divider string and capacitor array used for the successive

approximation conversion The voltage applied to this refer-

ence input defines the voltage span of the analog input (the

difference between VIN(MAX) and VIN(MIN) over which the

256 possible output codes apply) The reference source

must be capable of driving the reference input resistance

which can be as low as 13 kX

For absolute accuracy where the analog input varies be-

tween specific voltage limits the reference input must be

biased with a stable voltage source The ADC08234 and the

ADC08238 provide the output of a 25V band-gap reference

at VREFOUT This voltage does not vary appreciably with

temperature supply voltage or load current (see Reference

Characteristics in the Electrical Characteristics tables) and

can be tied directly to VREFIN for an analog input span of 0V

to 25V This output can also be used to bias external cir-

cuits and can therefore be used as the reference in ratio-

metric applications Bypassing VREFOUT with a 100 mF ca-

pacitor is recommended

For the ADC08231 the output of the on-board reference is

internally tied to the reference input Consequently the ana-

log input span for this device is set at 0V to 25V The pin

VREFC is provided for bypassing purposes and biasing ex-

ternal circuits as suggested above

The maximum value of the reference is limited to the VCC

supply voltage The minimum value however can be quite

small (see Typical Performance Characteristics) to allow di-

rect conversions of transducer outputs providing less than a

5V output span Particular care must be taken with regard to

noise pickup circuit layout and system error voltage sourc-

es when operating with a reduced span due to the in-

creased sensitivity of the converter (1 LSB equals VREF

256)

TLH11015 – 18

a) Ratiometric

TLH11015 – 19

b) Absolute

FIGURE 2 Reference Examples

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