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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M08045 датащи(PDF) 27 Page - M/A-COM Technology Solutions, Inc. |
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M08045 датащи(HTML) 27 Page - M/A-COM Technology Solutions, Inc. |
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27 / 49 page  Functional Description M08035, M08045 Data Sheet V1 MACOM ™ 27 080x5-DSH-001 On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 15 bits following SB and OP are used. On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or OP renders the operation undefined. The falling edge of xCS always resets the serial operation for a new Read or Write cycle. Detailed timing information is shown below. Figure 4-7. Four-Wire Sequential WRITE Table 4-4. Four-wire Interface Timing Timing Symbol Description Min Max Unit Tds Data set-up time 5 — ns Tdh Data hold time 5 — ns Tcs xCS set-up time 5 — ns Tch xCS hold time 5 — ns Tfreq, write Four-wire interface write clock frequency — 40 MHz Tfreq, read Four-wire interface clock read frequency, DVDDIO=2.5 V or 3.3 V —40 MHz Four-wire interface read clock frequency, DVDDIO=1.8 V — 20 MHz Four-wire interface read clock frequency, DVDDIO=1.2 V — 5 MHz TDUTY SCLK duty cycle 40 60 % Tdd Read data output delay (measured with max 30 pF loading, DVDDIO=3.3 V) 18 ns SCLK xCS 1 SI SO 2 3 ... 11 12 13 14 ... 20 21 Address[7:0] 1st Data[7:0] R/W 22 23 ... 29 30 2nd Data[7:0] 3rd Data[7:0] Tcs Tdh Tds 1 ... |
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