M08045 datasheet(22/49 Pages) MA-COM

22 / 49 page

Functional Description

M08035, M08045 Data Sheet V1

MACOM

™

080x5-DSH-001

A Loss of Signal (LOS) detector monitors each input and issues an alarm when the input signal level dips below the

detection threshold set in register 06h. See Section 4.3 for more information on the LOS circuit.

In order to correct any duty cycle distortion (DCD) in the input signal, or any DC offset buildup in the internal signal

path, a DC correction loop has been added. Programming register 0Dh bit 1 to a '1' will disable the DC correction

loop for all inputs.

The M08035/M08045 include a 4:1 multiplexer. This allows any one of the four input signals to be routed to the

reclocker. By default SDI0 is selected to be routed to SDO0. The selected input can be set using MUX control

By default, only the selected input is powered up, with all other inputs powered down. When an input is powered

down, its associated LOS circuitry is disabled. If required, all the other inputs can also be powered up by setting

bit[3] in register 0Dh. This will allow a faster response if rapid input switching is required as there is no delay waiting

for the circuitry to power-up and adjust to the input signal, but has the disadvantage of consuming more power.

With all inputs enabled, the power consumption increases by 100 mW.

4.3

LOS (Loss of Signal)

The M08035/M08045 have integrated LOS circuits on each of their four high-speed inputs. This circuit monitors the

input amplitude and if it falls below the detection threshold it asserts the LOS alarm bit by setting this to a logic

high. These alarm bits are latched and will need to be reset with the CLR_ALARMS, register 85h, by setting bit 0 to

a high and back to a low. Hysteresis is built into the LOS circuit to avoid chattering. The LOS threshold can be set

to a different level by using the bits[7:5] in register 06h, this changes the level on all four inputs.

By default, the LOS alarm mutes the signal from that particular input. Setting register 06h bit[3] to a high will disable

this feature.

Figure 4-3.

Self Biasing the Input of M08035/M08045

Upstream

Device

M08035 /M08045

AVDDI do not supply

a voltage

2.5V– 3.3V

AVDDO

DC coupled only,

Do not use internal

voltage regulator

0.1 µF per

AVDDI pin

NOTE:

For self bias applications, no voltage must be applied to the AVDDI pin. Every AVDDI pin should be decoupled to GND with a 0.1 µF

capacitor as shown in Figure 4-3.

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