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www.pericom.com

PI6LC48L0201

Rev. A

07/23/2013

PI6LC48L0201

2-Output LVDS Networking Clock Generator

Recommendations for Unused Input and Output Pins

Inputs:

Crystal Inputs:

For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. A 1kΩ

resistor can be tied from XTAL_IN to ground for additional protection.

Ref_IN Input:

For applications not requiring the use of the clock, it can be left floating. A 1kΩ resistor tied from the Ref_IN to ground can provide

additional protection.

LVCMOS Control Pins:

All control pins have internal pulldowns; A 1kΩ resistor tied from each control pin to ground can provide additional protection.

Outputs:

LVDS Outputs:

All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we

recommend that there is no trace attached.

Crystal Input Interface

The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below

were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.

C1

22pF

C2

22pF

XTAL_IN

XTAL_OUT

X1

18pF Parallel Crystal

13-0115