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www.pericom.com

PI6LC48L0201

Rev. A

07/23/2013

PI6LC48L0201

2-Output LVDS Networking Clock Generator

100Ω

Z = 50Ω

o

Z = 50Ω

o

LVDS Buffer

L = 0 ~ 10 in.

LVDS Test Circuit

Power Supply Filtering Techniques

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-

mance, power supply isolation is required. The PI6LC48L0201 provides separate power supplies to isolate any high switching noise

0.1µF

0.1µF

10µF

10Ω *

3.3V or 2.5V

13-0115