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ADC0819 датащи(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали ADC0819
подробное описание детали  8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer
PDF  12 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC0819 датащи(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
The following specifications apply for VCC e 5V VREF e 5V w2 CLK e 2097 MHz unless otherwise specified Boldface limits
apply from TMIN to TMAX all other limits TA e TJ e 25 C
Typical
Tested
Design
Parameter
Conditions
(Note 6)
Limit
Limit
Units
(Note 7)
(Note 8)
DIGITAL AND DC CHARACTERISTICS
(Continued)
VOUT(1) Logical ‘‘1’’
VCCe475V
Output Voltage (Min)
IOUTeb360 mA
24
24
V
IOUTeb10 mA
45
45
V
VOUT(0) Logical ‘‘0’’
VCCe525V
04
04
V
Output Voltage (Max)
IOUTe16 mA
IOUT TRI-STATE Output
VOUTe0V
b
001
b
3
b
3
m
A
Current (Max)
VOUTe5V
001
3
3
m
A
ISOURCE Output Source
VOUTe0V
b
14
b
65
b
65
mA
Current (Min)
ISINK Output Sink Current (Min)
VOUTeVCC
16
80
80
mA
ICC Supply Current (Max)
CSe1 VREF Open
1
25
25
mA
IREF (Max)
VREFe5V
07
1
1
mA
AC CHARACTERISTICS
Tested
Design
Parameter
Conditions
Typical
Limit
Limit
Units
(Note 6)
(Note 7)
(Note 8)
w CLK w Clock Frequency
MIN
10
MHz
MAX
21
SCLK Serial Data Clock
MIN
50
KHz
Frequency
MAX
525
TC Conversion Process Time
MIN
Not Including MUX
26
w
cycles
Addressing and
MAX
Analog Input
32
Sampling Times
tACC Access Time Delay From CS
MIN
1
w
cycles
Falling Edge to DO Data Valid
MAX
3
tSETUP Minimum Setup Time of CS Falling
4 w2CLKa
1
2SCLK
sec
Edge to SCLK Rising Edge
tHCS CS Hold Time After the Falling
0
ns
Edge of SCLK
t CS Total CS Low Time
MIN
tset-upa8SCLK
sec
MAX
t CS(min)a26 w2CLK
sec
tHDI Minimum DI Hold Time from
0
ns
SCLK Rising Edge
tHDO Minimum DO Hold Time from SCLK
RLe
k
10
ns
Falling Edge
CLe
pF
tSDI Minimum DI Setup Time to SCLK
400
ns
Rising Edge
tDDO Maximum Delay From SCLK
RLe
k
250
ns
Falling Edge to DO Data Valid
CLe
pF
tTRI Maximum DO Hold Time
RLe k
150
ns
CS Rising edge to DO TRISTATE
CLe
pF
3



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