2–20

2.9.3

VECINT: Vector Interrupt Register

any value to this register removes the vector and update the next vector value (if another interrupt is pending). Note

that the vector value is offset. Therefore, its value is in increments of two (bit-0 is set to 0). When no interrupt is

pending, the vector is set to 00h. (see Table 2–8: Vector Interrupt Values). As shown, the interrupt vector is divided

into two fields; I[2:0] and G[3:0]. The I-field defines the interrupt source within a group (on first come first served basis)

and the G-field, which defines the group number. Group G0 is the lowest and G15 is the highest priority.

7

6

5

4

3

210

G3

G2

G1

G0

I2

I1

I0

0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/O

BIT

NAME

RESET

FUNCTION

3–1

I[2:0]

000

This field defines the interrupt source in a given group. See Table 2–8: Vector Interrupt Values.

Bit-0 is always = 0, therefore, vector values will be offset by two.

7–4

G[3:0]

0000

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 2–8. Vector Interrupt Values

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE

0

0

00

No interrupt

1

0

10

NOT USED

1

1

12

Output endpoint-1

1

2

14

Output endpoint-2

1

3

16

Output endpoint-3

1

4–7

18–1E

NOT USED

2

0

20

NOT USED

2

1

22

Input endpoint-1

2

2

24

Input endpoint-2

2

3

26

Input endpoint-3

2

4–7

28–2E

NOT USED

3

0

30

STPOW packet received

3

1

32

SETUP packet received

3

2

34

PWON interrupt

3

3

36

PWOFF interrupt

3

4

38

RESR interrupt

3

5

3A

SUSR interrupt

3

6

3C

RSTR interrupt

3

7

3E

RESERVED

4

0

40

I2C TXE interrupt

4

1

42

I2C RXF interrupt

4

2

44

Input endpoint–0

4

3

46

Output endpoint–0

4

4–7

48

→ 4E

NOT USED

5–15

X

90

→ FE

NOT USED