2–4

2.2.5

WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1ms clock is provided. If this register is not accessed for a period of 32ms, the WDT

counter will reset the MCU. (See Figure 2–3, Reset Diagram). When the IDL bit in PCON is set, the WDT will be

suspended until an interrupt is detected. At this point, the IDL bit will be cleared and the WDT will resume operation.

7

6

5

4

3

210

WDE

WDR

RSV

RSV

RSV

RSV

RSV

WDT

R/W

R/W

R/O

R/O

R/O

R/O

R/O

W/O

BIT

NAME

RESET

FUNCTION

0

WDT

0

MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1 in a

period of 31ms, the WDT will reset the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit counter

using 1ms CLK). This bit is read as 0.

5–1

RSV

0

Reserved = 0

6

WDR

0

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog

timer reset.

WDR = 0

A power-up or USB reset occurred.

WDR = 1

A watchdog timeout reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no

effect.

7

WDE

0

Watchdog Timer Enable.

WDE = 0

This bit is cleared only on power-up, USB-reset (if enabled) or WDT reset.

WDE = 1

When MCU writes a 1 to this bit the WDT will start running. MCU cannot disable the WDT. Only

power up or USB reset (if enabled) can clear it. When MCU is in idle state (IDL = 1), the WDT is

suspended.

2.2.6

PCON: Power Control Register (at SFR 87h)

7

6

5

4

3

210

SMOD

RSV

RSV

RSV

GF1

GF0

RSV

IDL

R/W

R/O

R/O

R/O

R/W

R/W

R/O

R/W

BIT

NAME

RESET

FUNCTION

0

IDL

0

MCU idle mode bit. This bit can be set by MCU and is cleared only by INT1 interrupt.

IDL = 0

MCU is NOT in idle mode. This bit is cleared by INT1 interrupt logic when INT1 is asserted for

at least 400

µs.

IDL = 1

MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the WDT

will be suspended. When in suspend mode, only INT1 can be used to exit from idle mode and

generate an interrupt. INT1 must be asserted for at least 400

µs for the interrupt to be

recognized.

1

RSV

0

Reserved

3–2

GF[1:0]

00

General-purpose bits. MCU can write and read them.

6–4

RSV

0

Reserved

7

SMOD

0

Double baud rate control bit. For more information see UART serial interface in M8052 core specification.

2.3

Buffers + I/O RAM Map

The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB),

and all I/O. RAM space of 512 bytes [FD80–FF7F] is used for EDB and buffers. The FF80–FFFF range is used for

memory mapped registers (MMR). Table 2–1 represents the internal XDATA space allocation.