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SCD5028-2 Rev G 5/7/2014

Aeroflex Plainview

READING THE ACT 5028B

The Busy signal is asynchronous to the Read signal created by the interface circuit that reads it. Because of

the asynchronous nature of the system (inherent with other Resolver to Digital Converters) the designer

must be careful when reading the digital interface.

The implementation of reading the RDC is accomplished in one of two ways, using a CPU/MPU or using an

FPGA. The best method for reading the counter may also depend on the rep rate of the counter clock that

can vary from 0 to 1µS.

The Busy pulse is instrumental in reading stable data from the RDC5028. The Busy pulse will be present for

the following two situations:

1) When ever data is incremented or decremented in the RDC counter.

2) Directly after the trailing positive going edge of /INH (see A within example 5 timing diagram).

Based on 1 above there are many methods that can be implemented to synchronize the reading of data

from the RDC5028, below are a few examples:

Example 1: If the only time a read will occur is after the RDC has stopped (0 rps) there will be no

Busy signal to contend with.

Example 2: Knowing the Busy rep rate an Interrupt to a CPU or Logic can be developed from the

Busy pulse for the system to Read the RDC chip as long as the read is guaranteed to

occur prior to the next Busy pulse.

Example 3: As long as the resolver is rotating the Busy Pulse can be used to indicate stable data to

be sampled on leading or trailing edge.

Example 4: Ignore Busy and perform two reads back to back and compare, if they are equal you

have good data. The designer should be aware of the rep rate of Busy which is equal to

the clock rate of the counter. In most cases the angular velocity is < 3 rps in which case

like to be within 5µs of each other and the LSB would be ignored. Although this method

would be easier to implement with a CPU it could also be done in an FPGA.

Example 5: The circuit below ignores the Busy signal but insures sampling of stable data. The clock

should be a least 10MHz, the /RD pulse should be a minimum of 1.2µs (to insure

minimum /INH pulse width of 400ns), the sampling of data should be taken on the rising

edge of the signal /RD. The /RD signal is synced up with the CLK such that the sampling

on the D latch occurs on the opposite edge of the /RD transition.

/INH & /EN

Busy

Q

/Q

D

CK

CLK

Q

/Q

D

CK

/RD

S

S